first.qsf

verilog 初学者原代码

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		first_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240F100C5
set_global_assignment -name TOP_LEVEL_ENTITY first
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:18:55  APRIL 04, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP1"
set_global_assignment -name VERILOG_FILE first.v
set_global_assignment -name CUT_OFF_CLEAR_AND_PRESET_PATHS ON
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
set_global_assignment -name ENABLE_VREFB_PIN OFF
set_global_assignment -name ENABLE_VREFA_PIN OFF
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE OFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE OFF
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE ON
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT OFF
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT ON
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT OFF
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFF
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_global_assignment -name ENABLE_DEVICE_WIDE_OE OFF
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET OFF
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES OFF
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name USER_START_UP_CLOCK OFF
set_global_assignment -name SECURITY_BIT OFF
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM OFF
set_global_assignment -name AUTO_OPEN_DRAIN_PINS ON
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS OFF
set_global_assignment -name AUTO_FAST_INPUT_REGISTERS OFF
set_global_assignment -name AUTO_FAST_OUTPUT_REGISTERS OFF
set_global_assignment -name AUTO_GLOBAL_OE ON
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS ON
set_global_assignment -name AUTO_GLOBAL_CLOCK ON
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name SAVE_DISK_SPACE ON
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES OFF -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name END_TIME "1 us"
set_global_assignment -name CHECK_OUTPUTS OFF
set_global_assignment -name SETUP_HOLD_DETECTION ON
set_global_assignment -name START_TIME "0 ns"
set_global_assignment -name GLITCH_INTERVAL "0 ns"
set_global_assignment -name GLITCH_DETECTION OFF
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF
set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN "0 ns"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"