first.fit.rpt

verilog 初学者原代码

; LAB Constraint 'non-global controls' - Fit Attempt 1                           ;        ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ;        ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ;        ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ;        ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ;        ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ;        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ;        ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ;        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ;        ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ;        ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ;        ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ;        ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ;        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ;        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ;        ;
; LEs in Chains - Fit Attempt 1                                                  ; 0      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0      ;
; LABs with Chains - Fit Attempt 1                                               ; 0      ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0      ;
; Time - Fit Attempt 1                                                           ; 0      ;
+--------------------------------------------------------------------------------+--------+


+--------------------------------------------+
; Advanced Data - Placement                  ;
+------------------------------------+-------+
; Name                               ; Value ;
+------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff    ;
; Early Wire Use - Fit Attempt 1     ; 0     ;
; Early Slack - Fit Attempt 1        ; -5607 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff    ;
; Mid Wire Use - Fit Attempt 1       ; 0     ;
; Mid Slack - Fit Attempt 1          ; -4964 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Late Wire Use - Fit Attempt 1      ; 1     ;
; Late Slack - Fit Attempt 1         ; -4964 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff    ;
; Time - Fit Attempt 1               ; 0     ;
+------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -5968 ;
; Mid Slack - Fit Attempt 1           ; -5968 ;
; Late Slack - Fit Attempt 1          ; -5968 ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Peak Regional Wire - Fit Attempt 1  ; 0     ;
; Late Wire Use - Fit Attempt 1       ; 1     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Apr 04 23:17:10 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off first -c first
Info: Selected device EPM240F100C5 for design "first"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240F100I5 is compatible
    Info: Device EPM570F100C5 is compatible
    Info: Device EPM570F100I5 is compatible
Warning: No exact pin location assignment(s) for 16 pins of 16 total pins
    Info: Pin ledout[0] not assigned to an exact location on the device
    Info: Pin ledout[1] not assigned to an exact location on the device
    Info: Pin ledout[2] not assigned to an exact location on the device
    Info: Pin ledout[3] not assigned to an exact location on the device
    Info: Pin ledout[4] not assigned to an exact location on the device
    Info: Pin ledout[5] not assigned to an exact location on the device
    Info: Pin ledout[6] not assigned to an exact location on the device
    Info: Pin ledout[7] not assigned to an exact location on the device
    Info: Pin keyin[0] not assigned to an exact location on the device
    Info: Pin keyin[1] not assigned to an exact location on the device
    Info: Pin keyin[2] not assigned to an exact location on the device
    Info: Pin keyin[3] not assigned to an exact location on the device
    Info: Pin keyin[4] not assigned to an exact location on the device
    Info: Pin keyin[5] not assigned to an exact location on the device
    Info: Pin keyin[6] not assigned to an exact location on the device
    Info: Pin keyin[7] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  38 pins available
        Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is pin to pin delay of 4.715 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_B5; Fanout = 1; PIN Node = 'keyin[4]'
    Info: 2: + IC(1.261 ns) + CELL(2.322 ns) = 4.715 ns; Loc. = PIN_A2; Fanout = 0; PIN Node = 'ledout[4]'
    Info: Total cell delay = 3.454 ns ( 73.26 % )
    Info: Total interconnect delay = 1.261 ns ( 26.74 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
    Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Generated suppressed messages file E:/first/first.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 170 megabytes of memory during processing
    Info: Processing ended: Sat Apr 04 23:17:13 2009
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/first/first.fit.smsg.