first.v

来自「verilog 初学者原代码」· Verilog 代码 · 共 20 行

module first (keyin,ledout);
  // Port Declaration
	input [7:0] keyin;
  	output [7:0] ledout;

  // Wire Declaration

  // Integer Declaration
	reg [7:0] ledout_reg;
  // Concurent Assignment

  // Always Statement
	always @ (keyin)
		begin 
		ledout_reg=keyin;
		end
	assign ledout=ledout_reg; 
endmodule