📄 pll1.rpt
字号:
Dedicated Inputs:
Pin Type Code VCCIO I/O Standard Input Ref Current Name
2 INPUT - LVTTL - - fosc
43 INPUT - LVTTL - - fi
IOVCC group A: VCCIO Current is 0 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
4 INPUT - LVTTL - - reset
IOVCC group C: VCCIO Current is 8 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
28 OUTPUT 3.3V LVTTL - 4 ma ahead
29 OUTPUT 3.3V LVTTL - 4 ma lag
IOVCC group D: VCCIO Current is 4 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
41 OUTPUT 3.3V LVTTL - 4 ma fo
IOGND group A: GNDIO Current is 4 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
4 INPUT - LVTTL - - reset
41 OUTPUT - LVTTL - 4 ma fo
IOGND group B: GNDIO Current is 8 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
28 OUTPUT - LVTTL - 4 ma ahead
29 OUTPUT - LVTTL - 4 ma lag
Code:
/ = Slow slew-rate output
z = Pull-Up Resistor
b = Bus-Hold
Device-Specific Information: e:\myexample\pll\pll1.rpt
pll1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC28 ahead
| +--------------------- LC17 fo
| | +------------------- LC27 lag
| | | +----------------- LC26 :1
| | | | +--------------- LC25 |74163:26|p74163:sub|QA
| | | | | +------------- LC24 |74163:26|p74163:sub|QB
| | | | | | +----------- LC23 |74163:26|p74163:sub|QC
| | | | | | | +--------- LC22 |74163:26|p74163:sub|QD
| | | | | | | | +------- LC21 |74163:27|p74163:sub|QA
| | | | | | | | | +----- LC20 |74169:3|Q0
| | | | | | | | | | +--- LC19 |74169:3|Q1
| | | | | | | | | | | +- LC18 |74169:3|Q2
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> - * - * * * * * * - - - | - * | <-- fo
LC26 -> - - - - - - - - - - * * | - * | <-- :1
LC25 -> - * - - * * * * * - - - | - * | <-- |74163:26|p74163:sub|QA
LC24 -> - * - - - * * * * - - - | - * | <-- |74163:26|p74163:sub|QB
LC23 -> - * - - - - * * * - - - | - * | <-- |74163:26|p74163:sub|QC
LC22 -> - * - - * * * * * - - - | - * | <-- |74163:26|p74163:sub|QD
LC21 -> - * - - * * * * * - - - | - * | <-- |74163:27|p74163:sub|QA
LC20 -> * - - - * * - - - * * * | - * | <-- |74169:3|Q0
LC19 -> * - * - * * - - - * * * | - * | <-- |74169:3|Q1
LC18 -> * - * - * * - - - * * * | - * | <-- |74169:3|Q2
Pin
43 -> - - - - - - - - - * * - | - * | <-- fi
2 -> - - - - - - - - - - - - | - - | <-- fosc
4 -> - - - - - - - - - * * * | - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\myexample\pll\pll1.rpt
pll1
** EQUATIONS **
fi : INPUT;
fosc : INPUT;
reset : INPUT;
-- Node name is 'ahead'
-- Equation name is 'ahead', location is LC028, type is output.
ahead = LCELL( _EQ001 $ GND);
_EQ001 = _LC018 & _LC019 & _LC020;
-- Node name is 'fo' = '|74163:27|p74163:sub|QB'
-- Equation name is 'fo', type is output
fo = DFFE( _EQ002 $ GND, GLOBAL( fosc), VCC, VCC, VCC);
_EQ002 = !fo & _LC021 & _LC022 & _LC023 & _LC024 & _LC025
# fo & !_LC022
# fo & !_LC021;
-- Node name is 'lag'
-- Equation name is 'lag', location is LC027, type is output.
lag = LCELL( _EQ003 $ GND);
_EQ003 = !_LC018 & !_LC019;
-- Node name is '|74163:26|p74163:sub|:34' = '|74163:26|p74163:sub|QA'
-- Equation name is '_LC025', type is buried
_LC025 = DFFE( _EQ004 $ GND, GLOBAL( fosc), VCC, VCC, VCC);
_EQ004 = fo & _LC018 & _LC019 & _LC020 & _LC021 & _LC022
# fo & !_LC018 & !_LC019 & _LC021 & _LC022
# !_LC022 & !_LC025
# !_LC021 & !_LC025
# !fo & !_LC025;
-- Node name is '|74163:26|p74163:sub|:35' = '|74163:26|p74163:sub|QB'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( _EQ005 $ VCC, GLOBAL( fosc), VCC, VCC, VCC);
_EQ005 = fo & _LC018 & _LC019 & _LC020 & _LC021 & _LC022
# _LC024 & _LC025 & _X001
# !_LC024 & !_LC025 & _X001;
_X001 = EXP( fo & _LC021 & _LC022);
-- Node name is '|74163:26|p74163:sub|:36' = '|74163:26|p74163:sub|QC'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ006 $ GND, GLOBAL( fosc), VCC, VCC, VCC);
_EQ006 = fo & _LC021 & _LC022
# !_LC023 & _LC024 & _LC025
# _LC023 & !_LC024
# _LC023 & !_LC025;
-- Node name is '|74163:26|p74163:sub|:37' = '|74163:26|p74163:sub|QD'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( _EQ007, GLOBAL( fosc), VCC, VCC, VCC);
_EQ007 = _LC023 & _LC024 & _LC025
# fo & _LC021 & _LC022;
-- Node name is '|74163:27|p74163:sub|:34' = '|74163:27|p74163:sub|QA'
-- Equation name is '_LC021', type is buried
_LC021 = TFFE( _EQ008, GLOBAL( fosc), VCC, VCC, VCC);
_EQ008 = _LC022 & _LC023 & _LC024 & _LC025
# fo & _LC021 & _LC022;
-- Node name is '|74169:3|:3' = '|74169:3|Q0'
-- Equation name is '_LC020', type is buried
_LC020 = DFFE( _EQ009 $ fi, GLOBAL( fi), VCC, VCC, VCC);
_EQ009 = fi & _LC018 & !_LC019 & _LC020 & reset
# fi & !_LC018 & _LC019 & _LC020 & reset
# !fi & _LC018 & !_LC020 & reset
# !fi & _LC019 & !_LC020 & reset;
-- Node name is '|74169:3|:15' = '|74169:3|Q1'
-- Equation name is '_LC019', type is buried
_LC019 = DFFE( _EQ010 $ _EQ011, GLOBAL( fi), VCC, VCC, VCC);
_EQ010 = !_LC018 & _LC019 & _LC020 & _LC026 & reset & _X002 & _X003 &
_X004
# _LC018 & !_LC019 & _LC020 & !_LC026 & reset & _X002 & _X003 &
_X004
# _LC018 & !_LC019 & !_LC020 & _LC026 & reset & _X002 & _X003 &
_X004
# !fi & _LC018 & _LC019 & _LC020 & _X002 & _X003 & _X004;
_X002 = EXP(!fi & !_LC018 & !_LC019);
_X003 = EXP( _LC019 & !_LC020 & !_LC026 & reset);
_X004 = EXP(!fi & !reset);
_EQ011 = _X002 & _X003 & _X004;
_X002 = EXP(!fi & !_LC018 & !_LC019);
_X003 = EXP( _LC019 & !_LC020 & !_LC026 & reset);
_X004 = EXP(!fi & !reset);
-- Node name is '|74169:3|:29' = '|74169:3|Q2'
-- Equation name is '_LC018', type is buried
_LC018 = DFFE( _EQ012 $ VCC, GLOBAL( fi), VCC, VCC, VCC);
_EQ012 = _LC018 & !_LC019 & !_LC020 & !_LC026 & reset
# !_LC018 & _LC019 & !_LC020 & reset
# !_LC018 & _LC019 & !_LC026 & reset;
-- Node name is ':1'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( fo $ GND, GLOBAL( fi), VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\myexample\pll\pll1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000B' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,451K
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