📄 pll.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC29 ahead
| +----------------------------- LC32 ck169
| | +--------------------------- LC28 d0
| | | +------------------------- LC27 d1
| | | | +----------------------- LC26 d2
| | | | | +--------------------- LC25 |edge:72|:1
| | | | | | +------------------- LC30 lag
| | | | | | | +----------------- LC31 ld
| | | | | | | | +--------------- LC17 q0
| | | | | | | | | +------------- LC24 q1
| | | | | | | | | | +----------- LC18 q2
| | | | | | | | | | | +--------- LC19 q3
| | | | | | | | | | | | +------- LC21 q4
| | | | | | | | | | | | | +----- LC22 q5
| | | | | | | | | | | | | | +--- LC23 u/d
| | | | | | | | | | | | | | | +- LC20 :52
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC28 -> * - * * * * - - * - - - - - - - | - * | <-- d0
LC27 -> * - * * * * * - * * * * - - - - | - * | <-- d1
LC26 -> * - * * * * * - * * * * - - - - | - * | <-- d2
LC17 -> - - - - - - - - * * * * * * - - | - * | <-- q0
LC24 -> - - - - - - - - - * * * * * - - | - * | <-- q1
LC18 -> - - - - - - - - - - * * * * - - | - * | <-- q2
LC19 -> - - - - - * - * * * * * * * - - | - * | <-- q3
LC21 -> - - - - - * - * * * * * * * - - | - * | <-- q4
LC22 -> - - - - - * - * * * * * * * * - | - * | <-- q5
LC23 -> - - - * * - - - - - - - - - - - | - * | <-- u/d
LC20 -> - - - - - - - - - - - - - - * - | - * | <-- :52
Pin
4 -> - * * * * - - - - - - - - - - * | * * | <-- fi
43 -> - - - - - - - - - - - - - - - - | - - | <-- fosc
5 -> - - * * * - - - - - - - - - - - | - * | <-- reset
LC12 -> - * * * * * - - - - - - - - - - | - * | <-- |edge:72|out
LC4 -> - * * * * - - - - - - - - - - * | - * | <-- :59
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\myexample\pll\pll.rpt
pll
** EQUATIONS **
fi : INPUT;
fosc : INPUT;
reset : INPUT;
-- Node name is 'ahead'
-- Equation name is 'ahead', location is LC029, type is output.
ahead = LCELL( _EQ001 $ GND);
_EQ001 = d0 & d1 & d2;
-- Node name is 'ck169'
-- Equation name is 'ck169', location is LC032, type is output.
ck169 = LCELL( _EQ002 $ VCC);
_EQ002 = fi & _LC004 & !_LC012
# !fi & !_LC004 & !_LC012;
-- Node name is 'd0' = '|74169:3|Q0'
-- Equation name is 'd0', type is output
d0 = TFFE(!_EQ003, _EQ004, VCC, VCC, VCC);
_EQ003 = !d0 & !d1 & !d2
# !d0 & !reset;
_EQ004 = _X001 & _X002;
_X001 = EXP(!fi & !_LC004 & !_LC012);
_X002 = EXP( fi & _LC004 & !_LC012);
-- Node name is 'd1' = '|74169:3|Q1'
-- Equation name is 'd1', type is output
d1 = DFFE( _EQ005 $ GND, _EQ006, VCC, VCC, VCC);
_EQ005 = d0 & !d1 & d2 & reset & u/d
# d0 & d1 & !d2 & reset & !u/d
# !d0 & !d1 & d2 & reset & !u/d
# !d0 & d1 & reset & u/d;
_EQ006 = _X001 & _X002;
_X001 = EXP(!fi & !_LC004 & !_LC012);
_X002 = EXP( fi & _LC004 & !_LC012);
-- Node name is 'd2' = '|74169:3|Q2'
-- Equation name is 'd2', type is output
d2 = DFFE( _EQ007 $ VCC, _EQ008, VCC, VCC, VCC);
_EQ007 = !d0 & !d1 & d2 & reset & !u/d
# !d0 & d1 & !d2 & reset
# d1 & !d2 & reset & !u/d;
_EQ008 = _X001 & _X002;
_X001 = EXP(!fi & !_LC004 & !_LC012);
_X002 = EXP( fi & _LC004 & !_LC012);
-- Node name is 'lag'
-- Equation name is 'lag', location is LC030, type is output.
lag = LCELL( _EQ009 $ GND);
_EQ009 = !d1 & !d2;
-- Node name is 'ld'
-- Equation name is 'ld', location is LC031, type is output.
ld = LCELL( _EQ010 $ VCC);
_EQ010 = q3 & q4 & q5;
-- Node name is 'q0' = '|74163:26|p74163:sub|QA'
-- Equation name is 'q0', type is output
q0 = TFFE(!_EQ011, GLOBAL( fosc), VCC, VCC, VCC);
_EQ011 = d0 & d1 & d2 & !q0 & q3 & q4 & q5
# !d0 & d2 & q0 & q3 & q4 & q5
# d1 & !d2 & q0 & q3 & q4 & q5
# !d1 & d2 & q0 & q3 & q4 & q5
# !d1 & !d2 & !q0 & q3 & q4 & q5;
-- Node name is 'q1' = '|74163:26|p74163:sub|QB'
-- Equation name is 'q1', type is output
q1 = DFFE( _EQ012 $ VCC, GLOBAL( fosc), VCC, VCC, VCC);
_EQ012 = !d1 & !d2 & q3 & q4 & q5
# q0 & q1 & _X003
# !q0 & !q1 & _X003;
_X003 = EXP( q3 & q4 & q5);
-- Node name is 'q2' = '|74163:26|p74163:sub|QC'
-- Equation name is 'q2', type is output
q2 = DFFE( _EQ013 $ VCC, GLOBAL( fosc), VCC, VCC, VCC);
_EQ013 = !d1 & !d2 & q3 & q4 & q5
# q0 & q1 & q2 & _X003
# !q0 & !q2 & _X003
# !q1 & !q2 & _X003;
_X003 = EXP( q3 & q4 & q5);
-- Node name is 'q3' = '|74163:26|p74163:sub|QD'
-- Equation name is 'q3', type is output
q3 = TFFE( _EQ014, GLOBAL( fosc), VCC, VCC, VCC);
_EQ014 = q0 & q1 & q2 & q3 & !q5
# q0 & q1 & q2 & q3 & !q4
# d1 & q3 & q4 & q5
# d2 & q3 & q4 & q5
# q0 & q1 & q2 & !q3;
-- Node name is 'q4' = '|74163:27|p74163:sub|QA'
-- Equation name is 'q4', type is output
q4 = TFFE( _EQ015, GLOBAL( fosc), VCC, VCC, VCC);
_EQ015 = q0 & q1 & q2 & q3
# q3 & q4 & q5;
-- Node name is 'q5' = '|74163:27|p74163:sub|QB'
-- Equation name is 'q5', type is output
q5 = DFFE( _EQ016 $ GND, GLOBAL( fosc), VCC, VCC, VCC);
_EQ016 = q0 & q1 & q2 & q3 & q4 & !q5
# !q3 & q5
# !q4 & q5;
-- Node name is 'u/d' = ':1'
-- Equation name is 'u/d', type is output
u/d = DFFE( q5 $ GND, _LC020, VCC, VCC, VCC);
-- Node name is '|edge:72|:6' = '|edge:72|out'
-- Equation name is '_LC012', type is buried
_LC012 = DFFE( _LC025 $ GND, GLOBAL( fosc), VCC, VCC, VCC);
-- Node name is '|edge:72|:1'
-- Equation name is '_LC025', type is buried
_LC025 = DFFE( _EQ017 $ GND, GLOBAL( fosc), !_LC012, VCC, VCC);
_EQ017 = d0 & d1 & d2 & q3 & q4 & q5
# !d1 & !d2 & q3 & q4 & q5;
-- Node name is ':50'
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( fi $ GND);
-- Node name is ':52'
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( fi $ _LC004);
-- Node name is ':59'
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( _LC008 $ GND);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\myexample\pll\pll.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,021K
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