fenpin.v

来自「PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), F」· Verilog 代码 · 共 32 行

module fenpin(clk,reset,ahead,lag,fout,load);
input clk,reset,ahead,lag;
output fout;
output load;

reg[6:0] counter;
wire load;
reg[5:0] mod;

assign fout=counter[6];
always @(ahead or lag)
  case({ahead,lag})
    2'b01:mod=6'd33;
    2'b10:mod=6'd31;
    default:mod=6'd32;
  endcase
    
assign load=!(counter==7'b1011111);

always @(posedge clk or negedge reset)
  if(!reset)
    begin
      counter<=7'b010_0000;
    end
  else
    if(!load)
      counter<=mod;
    else
      counter<=counter+1;
endmodule