updown_counter.v

来自「PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), F」· Verilog 代码 · 共 32 行

module updown_counter(clk,reset,u_dn,ahead,lag,ldn);
input clk,reset,u_dn;
output ahead,lag;
output ldn;
wire ahead,lag;
wire ldn;
reg[5:0] counter;

parameter UP_COUNTER=6'd35;
parameter DOWN_COUNTER=6'd29;
assign ahead=(counter==UP_COUNTER);
assign lag=(counter==DOWN_COUNTER);
assign ldn=~(ahead|lag);

always@(posedge clk or negedge reset)
  if(!reset)
    begin
      counter<=6'd32;
    end
  else
    begin
      if(!ldn)
         counter<=6'd32;
      else
        if(u_dn)
          counter<=counter+1;
        else
          counter<=counter-1;
    end
endmodule