ram_256.fit.rpt

这是我自己写的一个小小的VERILOG程序

+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                         ;
+------------------------------------------------------------------+------------+
; Name                                                             ; Value      ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                 ; ff         ;
; Mid Wire Use - Fit Attempt 1                                     ; 0          ;
; Mid Slack - Fit Attempt 1                                        ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                              ; 1          ;
; LE/ALM Count - Fit Attempt 1                                     ; 1          ;
; LAB Count - Fit Attempt 1                                        ; 1          ;
; Outputs per Lab - Fit Attempt 1                                  ; 0.000      ;
; Inputs per LAB - Fit Attempt 1                                   ; 0.000      ;
; Global Inputs per LAB - Fit Attempt 1                            ; 0.000      ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1    ; 0:1        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1             ; 0:1        ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1               ; 0:1        ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1       ; 0:1        ;
; LAB Constraint 'global controls' - Fit Attempt 1                 ; 0:1        ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:1        ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:1        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1      ; 0:1        ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1                 ; 0:1        ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1          ; 0:1        ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1      ; 0:1        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1        ; 0:1        ;
; LEs in Chains - Fit Attempt 1                                    ; 0          ;
; LEs in Long Chains - Fit Attempt 1                               ; 0          ;
; LABs with Chains - Fit Attempt 1                                 ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                        ; 0          ;
; Time - Fit Attempt 1                                             ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1                              ; 0.016      ;
+------------------------------------------------------------------+------------+


+-----------------------------------------------+
; Advanced Data - Placement                     ;
+----------------------------------+------------+
; Name                             ; Value      ;
+----------------------------------+------------+
; Auto Fit Point 3 - Fit Attempt 1 ; ff         ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff         ;
; Mid Wire Use - Fit Attempt 1     ; 0          ;
; Mid Slack - Fit Attempt 1        ; 2147483639 ;
; Late Wire Use - Fit Attempt 1    ; 0          ;
; Late Slack - Fit Attempt 1       ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff         ;
; Time - Fit Attempt 1             ; 0          ;
+----------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Routing                          ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016      ;
+-------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Apr 24 20:00:16 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ram_256 -c ram_256
Info: Selected device EP2C8Q208C8 for design "ram_256"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5Q208C8 is compatible
    Info: Device EP2C5Q208I8 is compatible
    Info: Device EP2C8Q208I8 is compatible
Info: No exact pin location assignment(s) for 1 pins of 1 total pins
    Info: Pin rst not assigned to an exact location on the device
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 1 input, 0 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  30 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  35 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  34 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  36 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Apr 24 20:00:20 2009
    Info: Elapsed time: 00:00:05


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/qutus/ram_2561/ram_256.fit.smsg.