ram_256.map.summary

来自「这是我自己写的一个小小的VERILOG程序」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri Apr 24 20:00:13 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : ram_256
Top-level Entity Name : ram_256
Family : Cyclone II
Total logic elements : 0
Total registers : 0
Total pins : 1
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0