ram_256.map.qmsg

这是我自己写的一个小小的VERILOG程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 24 20:00:13 2009 " "Info: Processing started: Fri Apr 24 20:00:13 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ram_256 -c ram_256 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram_256 -c ram_256" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ram_256.v(9) " "Warning (10268): Verilog HDL information at ram_256.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "ram_256.v" "" { Text "F:/qutus/ram_2561/ram_256.v" 9 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_256.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram_256.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_256 " "Info: Found entity 1: ram_256" {  } { { "ram_256.v" "" { Text "F:/qutus/ram_2561/ram_256.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ram_256 " "Info: Elaborating entity \"ram_256\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "out ram_256.v(6) " "Warning (10036): Verilog HDL or VHDL warning at ram_256.v(6): object \"out\" assigned a value but never read" {  } { { "ram_256.v" "" { Text "F:/qutus/ram_2561/ram_256.v" 6 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_EMPTY_SHELL" "ram_256 " "Warning: Entity \"ram_256\" contains only dangling pins" {  } {  } 0 0 "Entity \"%1!s!\" contains only dangling pins" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "rst " "Warning: No output dependent on input pin \"rst\"" {  } { { "ram_256.v" "" { Text "F:/qutus/ram_2561/ram_256.v" 3 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "1 " "Info: Implemented 1 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "0 " "Info: Implemented 0 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 24 20:00:13 2009 " "Info: Processing ended: Fri Apr 24 20:00:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/qutus/ram_2561/ram_256.map.smsg " "Info: Generated suppressed messages file F:/qutus/ram_2561/ram_256.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}