subadd.tan.qmsg

一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 28 17:26:50 2009 " "Info: Processing started: Tue Apr 28 17:26:50 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off subadd -c subadd --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off subadd -c subadd --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "B\[0\] S\[3\] 16.025 ns Longest " "Info: Longest tpd from source pin \"B\[0\]\" to destination pin \"S\[3\]\" is 16.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns B\[0\] 1 PIN PIN_240 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 3; PIN Node = 'B\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { B[0] } "NODE_NAME" } } { "subadd.vhd" "" { Text "C:/Documents and Settings/zhang-sj07/My Documents/U盘/EDA/quartus2/2007011251/subadd/subadd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.402 ns) + CELL(0.590 ns) 7.467 ns LessThan0~265 2 COMB LC_X4_Y20_N6 1 " "Info: 2: + IC(5.402 ns) + CELL(0.590 ns) = 7.467 ns; Loc. = LC_X4_Y20_N6; Fanout = 1; COMB Node = 'LessThan0~265'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.992 ns" { B[0] LessThan0~265 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.114 ns) 8.019 ns LessThan0~267 3 COMB LC_X4_Y20_N1 3 " "Info: 3: + IC(0.438 ns) + CELL(0.114 ns) = 8.019 ns; Loc. = LC_X4_Y20_N1; Fanout = 3; COMB Node = 'LessThan0~267'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.552 ns" { LessThan0~265 LessThan0~267 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.590 ns) 9.063 ns LessThan0~266 4 COMB LC_X4_Y20_N4 6 " "Info: 4: + IC(0.454 ns) + CELL(0.590 ns) = 9.063 ns; Loc. = LC_X4_Y20_N4; Fanout = 6; COMB Node = 'LessThan0~266'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.044 ns" { LessThan0~267 LessThan0~266 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.826 ns) + CELL(0.442 ns) 10.331 ns Add0~242 5 COMB LC_X3_Y20_N9 3 " "Info: 5: + IC(0.826 ns) + CELL(0.442 ns) = 10.331 ns; Loc. = LC_X3_Y20_N9; Fanout = 3; COMB Node = 'Add0~242'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.268 ns" { LessThan0~266 Add0~242 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.575 ns) 11.336 ns Add0~234COUT1_259 6 COMB LC_X3_Y20_N1 2 " "Info: 6: + IC(0.430 ns) + CELL(0.575 ns) = 11.336 ns; Loc. = LC_X3_Y20_N1; Fanout = 2; COMB Node = 'Add0~234COUT1_259'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { Add0~242 Add0~234COUT1_259 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.416 ns Add0~236COUT1_261 7 COMB LC_X3_Y20_N2 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 11.416 ns; Loc. = LC_X3_Y20_N2; Fanout = 2; COMB Node = 'Add0~236COUT1_261'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~234COUT1_259 Add0~236COUT1_261 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 11.496 ns Add0~238COUT1_263 8 COMB LC_X3_Y20_N3 1 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 11.496 ns; Loc. = LC_X3_Y20_N3; Fanout = 1; COMB Node = 'Add0~238COUT1_263'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~236COUT1_261 Add0~238COUT1_263 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 12.104 ns Add0~239 9 COMB LC_X3_Y20_N4 1 " "Info: 9: + IC(0.000 ns) + CELL(0.608 ns) = 12.104 ns; Loc. = LC_X3_Y20_N4; Fanout = 1; COMB Node = 'Add0~239'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { Add0~238COUT1_263 Add0~239 } "NODE_NAME" } } { "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.797 ns) + CELL(2.124 ns) 16.025 ns S\[3\] 10 PIN PIN_4 0 " "Info: 10: + IC(1.797 ns) + CELL(2.124 ns) = 16.025 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'S\[3\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.921 ns" { Add0~239 S[3] } "NODE_NAME" } } { "subadd.vhd" "" { Text "C:/Documents and Settings/zhang-sj07/My Documents/U盘/EDA/quartus2/2007011251/subadd/subadd.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.678 ns ( 41.67 % ) " "Info: Total cell delay = 6.678 ns ( 41.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.347 ns ( 58.33 % ) " "Info: Total interconnect delay = 9.347 ns ( 58.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "16.025 ns" { B[0] LessThan0~265 LessThan0~267 LessThan0~266 Add0~242 Add0~234COUT1_259 Add0~236COUT1_261 Add0~238COUT1_263 Add0~239 S[3] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "16.025 ns" { B[0] {} B[0]~out0 {} LessThan0~265 {} LessThan0~267 {} LessThan0~266 {} Add0~242 {} Add0~234COUT1_259 {} Add0~236COUT1_261 {} Add0~238COUT1_263 {} Add0~239 {} S[3] {} } { 0.000ns 0.000ns 5.402ns 0.438ns 0.454ns 0.826ns 0.430ns 0.000ns 0.000ns 0.000ns 1.797ns } { 0.000ns 1.475ns 0.590ns 0.114ns 0.590ns 0.442ns 0.575ns 0.080ns 0.080ns 0.608ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Peak virtual memory: 126 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 28 17:26:51 2009 " "Info: Processing ended: Tue Apr 28 17:26:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}