m_00000000004170147728_1609310209.c

verilogHDL编写的QPSK选相法调制模块

    char *t140;
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    char *t688;

LAB0:    t0 = 1;

LAB2:    t3 = ((char*)((ng0)));
    t4 = (t1 + 10884);
    xsi_vlogvar_assign_value(t4, t3, 0, 0, 32);
    t3 = (t1 + 2148);
    t4 = *((char **)t3);
    t3 = (t1 + 10792);
    xsi_vlogvar_assign_value(t3, t4, 0, 0, 32);

LAB3:    t3 = (t1 + 10792);
    t4 = (t3 + 32U);
    t5 = *((char **)t4);
    t6 = ((char*)((ng0)));
    memset(t7, 0, 8);
    xsi_vlog_signed_greater(t7, 32, t5, 32, t6, 32);
    t8 = (t7 + 4U);
    t9 = *((unsigned int *)t8);
    t10 = (~(t9));
    t11 = *((unsigned int *)t7);
    t12 = (t11 & t10);
    t13 = (t12 != 0);
    if (t13 > 0)
        goto LAB4;

LAB5:    t3 = (t1 + 10884);