counterpart2.v

来自「an up down counter in verilog」· Verilog 代码 · 共 45 行

module counterPart2(in1,in2,in3,in4,count,      //semnale de intrare  
                    out1,out2,out3,out4);       //semnale de iesire 

parameter width=4;

input              in1,in2,in3,in4;
input [width-1:0]  count;

output             out1,out2,out3,out4;


wire               carryI,carryO1,carryO2;

sumator1bitNoCarryIn sumator1bitNoCarryInPart(.in1(count[0]),
                                              .in2(in1),
                                              .sum(out1),
                                              .carryOut(carryO1)
                                             );   


sumator1bit sumator1bitPart1(.in1(count[1]),
                             .in2(in2),
                             .carryIn(carryO1),
                             .sum(out2),
                             .carryOut(carryO2)   
                             );

sumator1bit sumator1bitPart2(.in1(count[2]),
                             .in2(in3),
                             .carryIn(carryO2),
                             .sum(out3),
                             .carryOut(carryI)   
                             );

sumator1bitNoCarryOut sumator1bitNoCarryOutPart(.in1(count[3]),
                                                .in2(in4),
                                                .carryIn(carryI),
                                                .sum(out4) 
                                                );

endmodule