test.v

来自「an up down counter in verilog」· Verilog 代码 · 共 59 行

module test();

parameter width=4;

reg in1,in2,in3,in4;
wire o1,o2,o3,o4;

wire tercnt;
reg reset,ck,ld;

wire [width-1:0] count;
reg  [width-1:0] data,count_to;


counterPart2 counterPart2test(.in1(in1),
                              .in2(in2),
			                       .in3(in3),
                     			      .in4(in4),
                     			      .count(count),
                     			      .out1(o1),
                      		      .out2(o2), 
                     			      .out3(o3),
                     			      .out4(o4)
                              );

counterPart3 counterPart3test(.ck(ck),
                              .ld(ld),
			      .data(data),
			      .count_to(count_to),
			      .reset(reset),
			      .in1(o1),
			      .in2(o2),
			      .in3(o3),
			      .in4(o4),
			      .count(count),
			      .tercnt(tercnt)
                               );

always #10 ck<=~ck;

initial
  begin ck<=0;
        count_to<=0; 
        data<=10000;
	in1<=1;
	in2<=0;
	in3<=0;
	in4<=0;
        
        #50 reset<=0;
            ld<='bx;

        #50 reset<=1; 
            ld<=0;
        
        #50 ld<=1; 
  end

endmodule