transcript

来自「an up down counter in verilog」· 代码 · 共 6 行

# Reading C:/Modeltech_5.5f/win32/../tcl/vsim/pref.tcl 
# vsim {G:\My} {Work\HDL} {Lab\Tema1\bistabil.v} 
# ERROR: Could not open library work at work: No such file or directory
# ERROR: Could not open library work at work: No such file or directory
# Error loading design