counterporti_test.v

来自「an up down counter in verilog」· Verilog 代码 · 共 32 行

module counterPorti_test();

parameter width=4;

wire               ck,ld,reset,cen,up_dn;     //input signals
wire  [width-1:0]  data,count_to; 

wire [width-1:0]  count;                      //output signals
wire              tercnt;

counterPorti #width counter_DUT(.ck(ck),
                                .reset(reset),
                                .ld(ld),
                                .cen(cen),
                                .up_dn(up_dn),
                                .data(data),
                                .count_to(count_to),
                                .count(count),
                                .tercnt(tercnt)
                                );

counterPorti_tb #width test(.data(data),
                            .count_to(count_to),
                            .up_dn(up_dn),
                            .ld(ld),
                            .cen(cen),
                            .ck(ck),
                            .reset(reset)
                            );

endmodule