udcounter_tb.v

an up down counter in verilog

//TEST BENCH UP_DOWN COUNTER

module UDCounter_tb(data,count_to,up_dn,ld,cen,ck,reset);   

parameter width=5;

output [width-1:0]  data,count_to;
output              up_dn,cen,ld,ck,reset;

reg    [width-1:0]  data,count_to;
reg                 up_dn,cen,ld,ck,reset;

always #10 ck<=~ck;

initial
  begin ck<=0;
        count_to<=0; 
        data<=10000;
        
        #50 reset<=0;
            ld<='bx;
            cen<='bx;
            up_dn<='bx;

        #50 reset<=1; 
            ld<=0;
        
        #50 ld<=1; 
            cen<=1;
            up_dn<=0;           
  end

endmodule