counterpart1.v

来自「an up down counter in verilog」· Verilog 代码 · 共 35 行

module counterPart1(cen,up_dn,      //semnale de intrare  
                    out);           //semnale de iesire 

parameter adun=0;

input cen,up_dn;

output out;

wire scadere;
assign scadere=1;
wire adunare;
assign adunare=adun;

wire zero;
assign zero=0;

wire out_cen_up_dn;
assign out_cen_up_dn = cen & up_dn; 

wire iesireMUX1;

mux21 mux21Part1a(.in1(scadere),
                  .in2(adunare),
                  .sel(out_cen_up_dn),
                  .out(iesireMUX1)
                  );

mux21 mux21Part1b(.in1(zero),
                  .in2(iesireMUX1),
                  .sel(cen),
                  .out(out)
                  );

endmodule