sumator1bitnocarryin.v

来自「an up down counter in verilog」· Verilog 代码 · 共 13 行

module sumator1bitNoCarryIn(in1,in2,             //semnale de intrare
                            sum,carryOut);       //semnale de iesire

input in1,in2;

output sum,carryOut;

wire out1,out2;

assign sum = in1 ^ in2;
assign carryOut = in1 & in2;

endmodule