bistabil.v

来自「an up down counter in verilog」· Verilog 代码 · 共 15 行

module bistabil(d,q,reset,ck);

input d,ck,reset;

output q;

reg q;

always@(posedge ck or negedge reset)
begin
  if(~reset) q<=1'b0;
        else q<=d;
end

endmodule