udcounter.v

来自「an up down counter in verilog」· Verilog 代码 · 共 37 行

//TABELUL DE ADEVAR PENTRU UP_DOWN COUNTER
//
//reset| load | cen | up_dn | Operation
//----------------------------------------
//  0  |  X   |  X  |   X   |   Reset
//  1  |  0   |  X  |   X   |   Load
//  1  |  1   |  0  |   X   |   Standby
//  1  |  1   |  1  |   0   |   Count down
//  1  |  1   |  1  |   1   |   Count up


module UDCounter(data,count_to,up_dn,ld,cen,ck,reset,  //semnale de intrare
                 count,tercnt);                        //semnale de iesire

parameter width=5;

input [width-1:0]  data,count_to;
input              up_dn,ld,cen;
input              ck;
input              reset;

output [width-1:0] count;
output             tercnt;

reg [width-1:0] count;

always @(posedge ck or negedge reset)
 if(~reset) count<=0;
    else if(~ld)count<=data;
            else if(cen)
                    if(up_dn) count<=count+1;
                       else count<=count-1;

assign tercnt=(count==count_to);
    
endmodule