sumator1bitnocarryout.v

来自「an up down counter in verilog」· Verilog 代码 · 共 13 行

module sumator1bitNoCarryOut(in1,in2,carryIn,   //semnale de intrare
                             sum);              //semnale de iesire

input in1,in2,carryIn;

output sum;

wire out1;

assign out1 = in1 ^ in2;
assign sum = out1 & carryIn;

endmodule