sumator1bit.v

来自「an up down counter in verilog」· Verilog 代码 · 共 17 行

module sumator1bit(in1,in2,carryIn,    //semnale de intrare
                   sum,carryOut);      //semnale de iesire

input in1,in2,carryIn;

output sum,carryOut;

wire out1,out2,out3;

assign out1 = in1 ^ in2;
assign out2 = in1 & in2;
assign out3 = out1 & carryIn;

assign sum = out1 ^ carryIn;
assign carryOut = out2 | out3;

endmodule