multiply.tlg

来自「a verilog programmed multiply unit algor」· TLG 代码 · 共 5 行

Selecting top level module multiply
Synthesizing module multiply
@W:"g:\my work\hdl lab\tema2\multiply.v":41:22:41:34|Edge and condition mismatch
@W:"g:\my work\hdl lab\tema2\multiply.v":41:0:41:5|Feedback mux created for signal iter[3:0]. Did you forget the set/reset assignment for this signal?