test.v

a verilog programmed multiply unit algorithm

module test();

parameter width=8;

wire [7:0] a,b;
wire ld,ck,reset,tercnt;
wire [15:0] produs;

multiply DUT(.ck(ck),
        		   .reset(reset),
             .ld(ld),
             .a(a),
	           .b(b),
          	  .produs(produs),
        		   .tercnt(tercnt)
	           );		

multiply_tb #width  TB(.ck(ck),
                       .reset(reset),
                       .ld(ld),
                       .a(a),
                       .b(b)
                       );

endmodule