divider_top.v

来自「a verilog programmed divide unit」· Verilog 代码 · 共 50 行

module divider (A, B, start, reset, ck, P, ready,reg_A);

input [7:0] A, B; 
input start, reset, ck; 
output [8:0] P;        
output ready; 
output [7:0] reg_A;       
                  
wire[7:0] A,B;
wire[8:0] P;
wire[7:0] reg_A;
wire start,ck,reset;
wire ready;
wire zero,msb_p,ld_A,shl_A,ld_B,ld_C,dec_C,ld_P,shl_P,clr_P;

calea_de_control CC(.start(start),
                    .ck(ck),
		                .reset(reset),
		              	.zero(zero),
		              	.msb_p(msb_p),
		              	.ld_A(ld_A),
		              	.shl_A(shl_A),
		              	.ld_B(ld_B),
			              .ld_C(ld_C),
		              	.dec_C(dec_C),
		              	.ld_P(ld_P),
		              	.shl_P(shl_P),
		              	.clr_P(clr_P),
		              	.ready(ready)
                    );

 cale_de_date CD(.A(A),
                 .B(B),
			           .P(P),
			            .reg_A(reg_A),
			           .ck(ck),
		             .reset(reset),
			           .zero(zero),
		           	 .msb_p(msb_p),
		           	 .ld_A(ld_A),
		          	 .shl_A(shl_A),
			           .ld_B(ld_B),
			           .ld_C(ld_C),
			           .dec_C(dec_C),
			           .ld_P(ld_P),
			           .shl_P(shl_P),
		           	.clr_P(clr_P));
		 
endmodule