test.v

a verilog programmed divide unit

module test ();

wire [7:0] A,B;
wire [8:0] P;  
wire [7:0] reg_A;
wire reset;   
wire start;   
wire ready;    
wire ck;      

div_TB TB (.A(A),
           .B(B),
	         .ck(ck),
	         .reset(reset),
	         .start(start)
           );

divider DUT  (.A(A),
              .B(B),
	            .P(P),
	            .reg_A(reg_A),
	            .ck(ck),
	            .reset(reset),
	            .start(start),
	            .ready(ready)); 
endmodule