div_tb.v

来自「a verilog programmed divide unit」· Verilog 代码 · 共 28 行

module div_TB(A,B,ck,reset,start);
parameter per=10;
output[7:0] A;
reg [7:0]   A;
output[7:0] B;
reg [7:0]   B;

output ck;
output reset,start;
reg ck,reset,start;

    initial
        begin
          reset<=0;
          ck<=0;
          start<=0;
          A<=8'd55;
          B<=8'd55;
          #35 reset<=1;
              start<=1;
          #35 start <=0;
              reset<=1;
	  #1000 $stop;//oprirea simularii dupa 1000ns 
        end

      always #per  ck <= ~ck;               
endmodule