prev_cmp_fcout.qmsg

基于Quartus II的8位十六进制频率计的项目设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 18 13:10:53 2009 " "Info: Processing started: Sat Apr 18 13:10:53 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off fcout -c fcout " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off fcout -c fcout" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vwf " "Info: Using vector source file \"E:/Quartus 2/quartus/a_Quar Projects/f_cout/fcout.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[0\] " "Info: Register: \|fcout\|cnt\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[1\] " "Info: Register: \|fcout\|cnt\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[2\] " "Info: Register: \|fcout\|cnt\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[3\] " "Info: Register: \|fcout\|cnt\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[4\] " "Info: Register: \|fcout\|cnt\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[5\] " "Info: Register: \|fcout\|cnt\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[6\] " "Info: Register: \|fcout\|cnt\[6\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[7\] " "Info: Register: \|fcout\|cnt\[7\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[9\] " "Info: Register: \|fcout\|cnt\[9\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[10\] " "Info: Register: \|fcout\|cnt\[10\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[8\] " "Info: Register: \|fcout\|cnt\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[11\] " "Info: Register: \|fcout\|cnt\[11\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[13\] " "Info: Register: \|fcout\|cnt\[13\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[15\] " "Info: Register: \|fcout\|cnt\[15\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[12\] " "Info: Register: \|fcout\|cnt\[12\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[14\] " "Info: Register: \|fcout\|cnt\[14\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[16\] " "Info: Register: \|fcout\|cnt\[16\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[18\] " "Info: Register: \|fcout\|cnt\[18\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[19\] " "Info: Register: \|fcout\|cnt\[19\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[17\] " "Info: Register: \|fcout\|cnt\[17\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[20\] " "Info: Register: \|fcout\|cnt\[20\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[23\] " "Info: Register: \|fcout\|cnt\[23\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[21\] " "Info: Register: \|fcout\|cnt\[21\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[22\] " "Info: Register: \|fcout\|cnt\[22\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[24\] " "Info: Register: \|fcout\|cnt\[24\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[26\] " "Info: Register: \|fcout\|cnt\[26\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[27\] " "Info: Register: \|fcout\|cnt\[27\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[25\] " "Info: Register: \|fcout\|cnt\[25\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[28\] " "Info: Register: \|fcout\|cnt\[28\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[29\] " "Info: Register: \|fcout\|cnt\[29\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|fcout\|cnt\[30\] " "Info: Register: \|fcout\|cnt\[30\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0 "" 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     19.57 % " "Info: Simulation coverage is      19.57 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "7207 " "Info: Number of transitions in simulation is 7207" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 18 13:10:55 2009 " "Info: Processing ended: Sat Apr 18 13:10:55 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}