count10.tan.qmsg

来自「基于Quartus II的十进制加法计数器的项目设计」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } } { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "e:/quartus 2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus 2/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[10\] register sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig 144.2 MHz 6.935 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 144.2 MHz between source register \"sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[10\]\" and destination register \"sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig\" (period= 6.935 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.674 ns + Longest register register " "Info: + Longest register to register delay is 6.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[10\] 1 REG LC_X22_Y6_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y6_N3; Fanout = 3; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[10\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.590 ns) 1.794 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~121 2 COMB LC_X22_Y6_N8 1 " "Info: 2: + IC(1.204 ns) + CELL(0.590 ns) = 1.794 ns; Loc. = LC_X22_Y6_N8; Fanout = 1; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~121'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.794 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~121 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.216 ns) + CELL(0.114 ns) 3.124 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~123 3 COMB LC_X21_Y8_N7 5 " "Info: 3: + IC(1.216 ns) + CELL(0.114 ns) = 3.124 ns; Loc. = LC_X21_Y8_N7; Fanout = 5; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~123'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~121 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~123 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.114 ns) 3.951 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~126 4 COMB LC_X22_Y8_N8 34 " "Info: 4: + IC(0.713 ns) + CELL(0.114 ns) = 3.951 ns; Loc. = LC_X22_Y8_N8; Fanout = 34; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~126'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.827 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~123 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~126 } "NODE_NAME" } } { "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus 2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.114 ns) 5.488 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address~11 5 COMB LC_X22_Y6_N2 1 " "Info: 5: + IC(1.423 ns) + CELL(0.114 ns) = 5.488 ns; Loc. = LC_X22_Y6_N2; Fanout = 1; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|base_address~11'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.537 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~126 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.478 ns) 6.674 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig 6 REG LC_X21_Y6_N6 2 " "Info: 6: + IC(0.708 ns) + CELL(0.478 ns) = 6.674 ns; Loc. = LC_X21_Y6_N6; Fanout = 2; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.186 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.410 ns ( 21.13 % ) " "Info: Total cell delay = 1.410 ns ( 21.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.264 ns ( 78.87 % ) " "Info: Total interconnect delay = 5.264 ns ( 78.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.674 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~121 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~123 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~126 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.674 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~121 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~123 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~126 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 1.204ns 1.216ns 0.713ns 1.423ns 0.708ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.909 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 253 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 253; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig 2 REG LC_X21_Y6_N6 2 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X21_Y6_N6; Fanout = 2; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|is_buffer_wrapped_once_sig'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { CLK {} CLK~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.909 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 253 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 253; CLK Node = 'CLK'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "count10.vhd" "" { Text "E:/Quartus 2/quartus/a_Quar Projects/count10/count10.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[10\] 2 REG LC_X22_Y6_N3 3 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X22_Y6_N3; Fanout = 3; REG Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[10\]'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] } "NODE_NAME" } } { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { CLK {} CLK~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { CLK {} CLK~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { CLK {} CLK~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 109 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "6.674 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~121 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~123 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~126 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "6.674 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~121 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~123 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~126 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address~11 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 1.204ns 1.216ns 0.713ns 1.423ns 0.708ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 0.478ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { CLK {} CLK~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { CLK {} CLK~out0 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo_reg 101.34 MHz 9.868 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 101.34 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 9.868 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.643 ns + Longest register register " "Info: + Longest register to register delay is 4.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LC_X12_Y14_N9 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y14_N9; Fanout = 21; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.431 ns) + CELL(0.590 ns) 2.021 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31 2 COMB LC_X13_Y12_N0 5 " "Info: 2: + IC(1.431 ns) + CELL(0.590 ns) = 2.021 ns; Loc. = LC_X13_Y12_N0; Fanout = 5; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~31'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "2.021 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_signaltap.vhd" 803 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.317 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~62 3 COMB LC_X13_Y12_N1 18 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.317 ns; Loc. = LC_X13_Y12_N1; Fanout = 18; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~62'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_signaltap.vhd" 831 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.114 ns) 2.848 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 4 COMB LC_X13_Y12_N8 1 " "Info: 4: + IC(0.417 ns) + CELL(0.114 ns) = 2.848 ns; Loc. = LC_X13_Y12_N8; Fanout = 1; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.531 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.442 ns) 3.698 ns sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 5 COMB LC_X13_Y12_N3 1 " "Info: 5: + IC(0.408 ns) + CELL(0.442 ns) = 3.698 ns; Loc. = LC_X13_Y12_N3; Fanout = 1; COMB Node = 'sld_signaltap:count10\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.850 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_signaltap.vhd" 512 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.994 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 6 COMB LC_X13_Y12_N4 1 " "Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 3.994 ns; Loc. = LC_X13_Y12_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.309 ns) 4.643 ns sld_hub:sld_hub_inst\|hub_tdo_reg 7 REG LC_X13_Y12_N5 2 " "Info: 7: + IC(0.340 ns) + CELL(0.309 ns) = 4.643 ns; Loc. = LC_X13_Y12_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "0.649 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.683 ns ( 36.25 % ) " "Info: Total cell delay = 1.683 ns ( 36.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.960 ns ( 63.75 % ) " "Info: Total interconnect delay = 2.960 ns ( 63.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.643 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "4.643 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.431ns 0.182ns 0.417ns 0.408ns 0.182ns 0.340ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.442ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.030 ns - Smallest " "Info: - Smallest clock skew is -0.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 279 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 279; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X13_Y12_N5 2 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X13_Y12_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.44 % ) " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns ( 86.56 % ) " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.322 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 279 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 279; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.611 ns) + CELL(0.711 ns) 5.322 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 2 REG LC_X12_Y14_N9 21 " "Info: 2: + IC(4.611 ns) + CELL(0.711 ns) = 5.322 ns; Loc. = LC_X12_Y14_N9; Fanout = 21; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.36 % ) " "Info: Total cell delay = 0.711 ns ( 13.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.611 ns ( 86.64 % ) " "Info: Total interconnect delay = 4.611 ns ( 86.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 393 -1 0 } } { "../../libraries/megafunctions/sld_hub.vhd" "" { Text "E:/Quartus 2/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "4.643 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "4.643 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~31 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~62 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 1.431ns 0.182ns 0.417ns 0.408ns 0.182ns 0.340ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.442ns 0.114ns 0.309ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.581ns } { 0.000ns 0.711ns } "" } } { "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus 2/quartus/bin/TimingClosureFloorplan.fld" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus 2/quartus/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|jtag_debug_mode_usr1 {} } { 0.000ns 4.611ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}