count10.tan.rpt

基于Quartus II的十进制加法计数器的项目设计

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                               ; To                                                                                                                                ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 5.933 ns                         ; EN                                                                                                                 ; CQI[2]                                                                                                                            ; --                           ; CLK                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 10.217 ns                        ; CQI[2]                                                                                                             ; COUT                                                                                                                              ; CLK                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 7.757 ns                         ; EN                                                                                                                 ; altera_count10_EN_ae                                                                                                              ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.586 ns                         ; altera_internal_jtag~TDIUTAP                                                                                       ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                                                                        ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 101.34 MHz ( period = 9.868 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                          ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 144.20 MHz ( period = 6.935 ns ) ; sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[10] ; sld_signaltap:count10|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|is_buffer_wrapped_once_sig ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                    ;                                                                                                                                   ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+