sreg8b.map.rpt

用VHDL语言仿真乘法器设计。能够实现一般乘法运算。

+----------------------------------+-----------------+------------------------------------+-------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path        ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------+
; sreg8b.vhd                       ; yes             ; User VHDL File                     ; D:/eda设计/VHDL/乘法器/sreg8b.vhd   ;
; andarith.vhd                     ; yes             ; User VHDL File                     ; D:/eda设计/VHDL/乘法器/andarith.vhd ;
; reg16b.vhd                       ; yes             ; User VHDL File                     ; D:/eda设计/VHDL/乘法器/reg16b.vhd   ;
; arictl.vhd                       ; yes             ; User VHDL File                     ; D:/eda设计/VHDL/乘法器/arictl.vhd   ;
; multi8x8.bdf                     ; yes             ; User Block Diagram/Schematic File  ; D:/eda设计/VHDL/乘法器/multi8x8.bdf ;
; adder8b.vhd                      ; yes             ; Other                              ; D:/eda设计/VHDL/乘法器/adder8b.vhd  ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 37      ;
; Total combinational functions     ; 29      ;
;     -- Total 4-input functions    ; 1       ;
;     -- Total 3-input functions    ; 11      ;
;     -- Total 2-input functions    ; 16      ;
;     -- Total 1-input functions    ; 0       ;
;     -- Total 0-input functions    ; 1       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 29      ;
; Total logic cells in carry chains ; 9       ;
; I/O pins                          ; 35      ;
; Maximum fan-out node              ; start   ;
; Maximum fan-out                   ; 29      ;
; Total fan-out                     ; 152     ;
; Average fan-out                   ; 2.11    ;
+-----------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
; |multi8x8                  ; 37 (0)      ; 29           ; 0           ; 35   ; 0            ; 8 (0)        ; 8 (0)             ; 21 (0)           ; 9 (0)           ; |multi8x8                ;
;    |andarith:inst1|        ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |multi8x8|andarith:inst1 ;
;    |arictl:inst2|          ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; |multi8x8|arictl:inst2   ;
;    |reg16b:inst3|          ; 16 (16)     ; 16           ; 0           ; 0    ; 0            ; 0 (0)        ; 7 (7)             ; 9 (9)            ; 9 (9)           ; |multi8x8|reg16b:inst3   ;
;    |sreg8b:inst4|          ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 7 (7)            ; 0 (0)           ; |multi8x8|sreg8b:inst4   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 20    ;
; Number of registers using Asynchronous Load  ; 1     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/eda设计/VHDL/乘法器/sreg8b.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 31 11:29:34 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sreg8b -c sreg8b
Info: Found 2 design units, including 1 entities, in source file sreg8b.vhd
    Info: Found design unit 1: sreg8b-behav
    Info: Found entity 1: sreg8b
Info: Found 2 design units, including 1 entities, in source file andarith.vhd
    Info: Found design unit 1: andarith-behav
    Info: Found entity 1: andarith
Info: Found 2 design units, including 1 entities, in source file reg16b.vhd
    Info: Found design unit 1: reg16b-behav
    Info: Found entity 1: reg16b
Info: Found 2 design units, including 1 entities, in source file arictl.vhd
    Info: Found design unit 1: arictl-behav
    Info: Found entity 1: arictl
Info: Found 1 design units, including 1 entities, in source file multi8x8.bdf
    Info: Found entity 1: multi8x8
Info: Elaborating entity "multi8x8" for the top level hierarchy
Info: Elaborating entity "arictl" for hierarchy "arictl:inst2"
Info: Elaborating entity "reg16b" for hierarchy "reg16b:inst3"
Info: Using design file adder8b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: adder8b-behav
    Info: Found entity 1: adder8b
Info: Elaborating entity "adder8b" for hierarchy "adder8b:inst"
Info: Elaborating entity "andarith" for hierarchy "andarith:inst1"
Info: Elaborating entity "sreg8b" for hierarchy "sreg8b:inst4"
Warning: Reduced register "arictl:inst2|cnt4b[3]" with stuck data_in port to stuck value GND
Info: Implemented 72 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 17 output pins
    Info: Implemented 37 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Dec 31 11:29:37 2007
    Info: Elapsed time: 00:00:03