sreg8b.map.eqn

用VHDL语言仿真乘法器设计。能够实现一般乘法运算。

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--D1_ariend is arictl:inst2|ariend
--operation mode is normal

D1_ariend_lut_out = D1_cnt4b[2] & D1_cnt4b[1] & D1_cnt4b[0];
D1_ariend = DFFEAS(D1_ariend_lut_out, clk, !start, , , , , , );


--E1_r16s[15] is reg16b:inst3|r16s[15]
--operation mode is normal

E1_r16s[15]_carry_eqn = E1L42;
E1_r16s[15]_lut_out = !E1_r16s[15]_carry_eqn;
E1_r16s[15] = DFFEAS(E1_r16s[15]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[14] is reg16b:inst3|r16s[14]
--operation mode is arithmetic

E1_r16s[14]_carry_eqn = E1L22;
E1_r16s[14]_lut_out = C1L8 $ E1_r16s[15] $ E1_r16s[14]_carry_eqn;
E1_r16s[14] = DFFEAS(E1_r16s[14]_lut_out, D1_clkout, !start, , , , , , );

--E1L42 is reg16b:inst3|r16s[14]~82
--operation mode is arithmetic

E1L42 = CARRY(C1L8 & !E1_r16s[15] & !E1L22 # !C1L8 & (!E1L22 # !E1_r16s[15]));


--E1_r16s[13] is reg16b:inst3|r16s[13]
--operation mode is arithmetic

E1_r16s[13]_carry_eqn = E1L02;
E1_r16s[13]_lut_out = C1L7 $ E1_r16s[14] $ !E1_r16s[13]_carry_eqn;
E1_r16s[13] = DFFEAS(E1_r16s[13]_lut_out, D1_clkout, !start, , , , , , );

--E1L22 is reg16b:inst3|r16s[13]~86
--operation mode is arithmetic

E1L22 = CARRY(C1L7 & (E1_r16s[14] # !E1L02) # !C1L7 & E1_r16s[14] & !E1L02);


--E1_r16s[12] is reg16b:inst3|r16s[12]
--operation mode is arithmetic

E1_r16s[12]_carry_eqn = E1L81;
E1_r16s[12]_lut_out = C1L6 $ E1_r16s[13] $ E1_r16s[12]_carry_eqn;
E1_r16s[12] = DFFEAS(E1_r16s[12]_lut_out, D1_clkout, !start, , , , , , );

--E1L02 is reg16b:inst3|r16s[12]~90
--operation mode is arithmetic

E1L02 = CARRY(C1L6 & !E1_r16s[13] & !E1L81 # !C1L6 & (!E1L81 # !E1_r16s[13]));


--E1_r16s[11] is reg16b:inst3|r16s[11]
--operation mode is arithmetic

E1_r16s[11]_carry_eqn = E1L61;
E1_r16s[11]_lut_out = C1L5 $ E1_r16s[12] $ !E1_r16s[11]_carry_eqn;
E1_r16s[11] = DFFEAS(E1_r16s[11]_lut_out, D1_clkout, !start, , , , , , );

--E1L81 is reg16b:inst3|r16s[11]~94
--operation mode is arithmetic

E1L81 = CARRY(C1L5 & (E1_r16s[12] # !E1L61) # !C1L5 & E1_r16s[12] & !E1L61);


--E1_r16s[10] is reg16b:inst3|r16s[10]
--operation mode is arithmetic

E1_r16s[10]_carry_eqn = E1L41;
E1_r16s[10]_lut_out = C1L4 $ E1_r16s[11] $ E1_r16s[10]_carry_eqn;
E1_r16s[10] = DFFEAS(E1_r16s[10]_lut_out, D1_clkout, !start, , , , , , );

--E1L61 is reg16b:inst3|r16s[10]~98
--operation mode is arithmetic

E1L61 = CARRY(C1L4 & !E1_r16s[11] & !E1L41 # !C1L4 & (!E1L41 # !E1_r16s[11]));


--E1_r16s[9] is reg16b:inst3|r16s[9]
--operation mode is arithmetic

E1_r16s[9]_carry_eqn = E1L21;
E1_r16s[9]_lut_out = C1L3 $ E1_r16s[10] $ !E1_r16s[9]_carry_eqn;
E1_r16s[9] = DFFEAS(E1_r16s[9]_lut_out, D1_clkout, !start, , , , , , );

--E1L41 is reg16b:inst3|r16s[9]~102
--operation mode is arithmetic

E1L41 = CARRY(C1L3 & (E1_r16s[10] # !E1L21) # !C1L3 & E1_r16s[10] & !E1L21);


--E1_r16s[8] is reg16b:inst3|r16s[8]
--operation mode is arithmetic

E1_r16s[8]_carry_eqn = E1L01;
E1_r16s[8]_lut_out = C1L2 $ E1_r16s[9] $ E1_r16s[8]_carry_eqn;
E1_r16s[8] = DFFEAS(E1_r16s[8]_lut_out, D1_clkout, !start, , , , , , );

--E1L21 is reg16b:inst3|r16s[8]~106
--operation mode is arithmetic

E1L21 = CARRY(C1L2 & !E1_r16s[9] & !E1L01 # !C1L2 & (!E1L01 # !E1_r16s[9]));


--E1_r16s[7] is reg16b:inst3|r16s[7]
--operation mode is arithmetic

E1_r16s[7]_lut_out = C1L1 $ E1_r16s[8];
E1_r16s[7] = DFFEAS(E1_r16s[7]_lut_out, D1_clkout, !start, , , , , , );

--E1L01 is reg16b:inst3|r16s[7]~110
--operation mode is arithmetic

E1L01 = CARRY(C1L1 & E1_r16s[8]);


--E1_r16s[6] is reg16b:inst3|r16s[6]
--operation mode is normal

E1_r16s[6]_lut_out = E1_r16s[7];
E1_r16s[6] = DFFEAS(E1_r16s[6]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[5] is reg16b:inst3|r16s[5]
--operation mode is normal

E1_r16s[5]_lut_out = E1_r16s[6];
E1_r16s[5] = DFFEAS(E1_r16s[5]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[4] is reg16b:inst3|r16s[4]
--operation mode is normal

E1_r16s[4]_lut_out = E1_r16s[5];
E1_r16s[4] = DFFEAS(E1_r16s[4]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[3] is reg16b:inst3|r16s[3]
--operation mode is normal

E1_r16s[3]_lut_out = E1_r16s[4];
E1_r16s[3] = DFFEAS(E1_r16s[3]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[2] is reg16b:inst3|r16s[2]
--operation mode is normal

E1_r16s[2]_lut_out = E1_r16s[3];
E1_r16s[2] = DFFEAS(E1_r16s[2]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[1] is reg16b:inst3|r16s[1]
--operation mode is normal

E1_r16s[1]_lut_out = E1_r16s[2];
E1_r16s[1] = DFFEAS(E1_r16s[1]_lut_out, D1_clkout, !start, , , , , , );


--E1_r16s[0] is reg16b:inst3|r16s[0]
--operation mode is normal

E1_r16s[0]_lut_out = E1_r16s[1];
E1_r16s[0] = DFFEAS(E1_r16s[0]_lut_out, D1_clkout, !start, , , , , , );


--D1_cnt4b[2] is arictl:inst2|cnt4b[2]
--operation mode is normal

D1_cnt4b[2]_lut_out = D1_cnt4b[2] # D1_cnt4b[1] & D1_cnt4b[0];
D1_cnt4b[2] = DFFEAS(D1_cnt4b[2]_lut_out, clk, !start, , , , , , );


--D1_cnt4b[1] is arictl:inst2|cnt4b[1]
--operation mode is normal

D1_cnt4b[1]_lut_out = D1_cnt4b[1] & (D1_cnt4b[2] # !D1_cnt4b[0]) # !D1_cnt4b[1] & (D1_cnt4b[0]);
D1_cnt4b[1] = DFFEAS(D1_cnt4b[1]_lut_out, clk, !start, , , , , , );


--D1_cnt4b[0] is arictl:inst2|cnt4b[0]
--operation mode is normal

D1_cnt4b[0]_lut_out = D1_cnt4b[2] & D1_cnt4b[1] # !D1_cnt4b[0];
D1_cnt4b[0] = DFFEAS(D1_cnt4b[0]_lut_out, clk, !start, , , , , , );


--D1_clkout is arictl:inst2|clkout
--operation mode is normal

D1_clkout_lut_out = clk & (!D1_cnt4b[0] # !D1_cnt4b[2] # !D1_cnt4b[1]);
D1_clkout = DFFEAS(D1_clkout_lut_out, clk, VCC, , , clk, start, , );


--F1_reg8[0] is sreg8b:inst4|reg8[0]
--operation mode is normal

F1_reg8[0]_lut_out = start & a[0] # !start & (F1_reg8[1]);
F1_reg8[0] = DFFEAS(F1_reg8[0]_lut_out, D1_clkout, VCC, , , , , , );


--C1L8 is andarith:inst1|dout[7]~80
--operation mode is normal

C1L8 = F1_reg8[0] & b[7];


--C1L7 is andarith:inst1|dout[6]~81
--operation mode is normal

C1L7 = F1_reg8[0] & b[6];


--C1L6 is andarith:inst1|dout[5]~82
--operation mode is normal

C1L6 = F1_reg8[0] & b[5];


--C1L5 is andarith:inst1|dout[4]~83
--operation mode is normal

C1L5 = F1_reg8[0] & b[4];


--C1L4 is andarith:inst1|dout[3]~84
--operation mode is normal

C1L4 = F1_reg8[0] & b[3];


--C1L3 is andarith:inst1|dout[2]~85
--operation mode is normal

C1L3 = F1_reg8[0] & b[2];


--C1L2 is andarith:inst1|dout[1]~86
--operation mode is normal

C1L2 = F1_reg8[0] & b[1];


--C1L1 is andarith:inst1|dout[0]~87
--operation mode is normal

C1L1 = F1_reg8[0] & b[0];


--F1_reg8[1] is sreg8b:inst4|reg8[1]
--operation mode is normal

F1_reg8[1]_lut_out = start & a[1] # !start & (F1_reg8[2]);
F1_reg8[1] = DFFEAS(F1_reg8[1]_lut_out, D1_clkout, VCC, , , , , , );


--F1_reg8[2] is sreg8b:inst4|reg8[2]
--operation mode is normal

F1_reg8[2]_lut_out = start & a[2] # !start & (F1_reg8[3]);
F1_reg8[2] = DFFEAS(F1_reg8[2]_lut_out, D1_clkout, VCC, , , , , , );


--F1_reg8[3] is sreg8b:inst4|reg8[3]
--operation mode is normal

F1_reg8[3]_lut_out = start & a[3] # !start & (F1_reg8[4]);
F1_reg8[3] = DFFEAS(F1_reg8[3]_lut_out, D1_clkout, VCC, , , , , , );


--F1_reg8[4] is sreg8b:inst4|reg8[4]
--operation mode is normal

F1_reg8[4]_lut_out = start & a[4] # !start & (F1_reg8[5]);
F1_reg8[4] = DFFEAS(F1_reg8[4]_lut_out, D1_clkout, VCC, , , , , , );


--F1_reg8[5] is sreg8b:inst4|reg8[5]
--operation mode is normal

F1_reg8[5]_lut_out = start & a[5] # !start & (F1_reg8[6]);
F1_reg8[5] = DFFEAS(F1_reg8[5]_lut_out, D1_clkout, VCC, , , , , , );


--F1_reg8[6] is sreg8b:inst4|reg8[6]
--operation mode is normal

F1_reg8[6]_lut_out = start & a[6] # !start & (F1_reg8[7]);
F1_reg8[6] = DFFEAS(F1_reg8[6]_lut_out, D1_clkout, VCC, , , , , , );


--F1_reg8[7] is sreg8b:inst4|reg8[7]
--operation mode is normal

F1_reg8[7]_lut_out = a[7];
F1_reg8[7] = DFFEAS(F1_reg8[7]_lut_out, D1_clkout, VCC, , start, , , , );


--clk is clk
--operation mode is input

clk = INPUT();


--start is start
--operation mode is input

start = INPUT();


--b[7] is b[7]
--operation mode is input

b[7] = INPUT();


--b[6] is b[6]
--operation mode is input

b[6] = INPUT();


--b[5] is b[5]
--operation mode is input

b[5] = INPUT();


--b[4] is b[4]
--operation mode is input

b[4] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--a[4] is a[4]
--operation mode is input

a[4] = INPUT();


--a[5] is a[5]
--operation mode is input

a[5] = INPUT();


--a[6] is a[6]
--operation mode is input

a[6] = INPUT();


--a[7] is a[7]
--operation mode is input

a[7] = INPUT();


--arictl is arictl
--operation mode is output

arictl = OUTPUT(D1_ariend);


--dout[15] is dout[15]
--operation mode is output

dout[15] = OUTPUT(E1_r16s[15]);


--dout[14] is dout[14]
--operation mode is output

dout[14] = OUTPUT(E1_r16s[14]);


--dout[13] is dout[13]
--operation mode is output

dout[13] = OUTPUT(E1_r16s[13]);


--dout[12] is dout[12]
--operation mode is output

dout[12] = OUTPUT(E1_r16s[12]);


--dout[11] is dout[11]
--operation mode is output

dout[11] = OUTPUT(E1_r16s[11]);


--dout[10] is dout[10]
--operation mode is output

dout[10] = OUTPUT(E1_r16s[10]);


--dout[9] is dout[9]
--operation mode is output

dout[9] = OUTPUT(E1_r16s[9]);


--dout[8] is dout[8]
--operation mode is output

dout[8] = OUTPUT(E1_r16s[8]);


--dout[7] is dout[7]
--operation mode is output

dout[7] = OUTPUT(E1_r16s[7]);


--dout[6] is dout[6]
--operation mode is output

dout[6] = OUTPUT(E1_r16s[6]);


--dout[5] is dout[5]
--operation mode is output

dout[5] = OUTPUT(E1_r16s[5]);


--dout[4] is dout[4]
--operation mode is output

dout[4] = OUTPUT(E1_r16s[4]);


--dout[3] is dout[3]
--operation mode is output

dout[3] = OUTPUT(E1_r16s[3]);


--dout[2] is dout[2]
--operation mode is output

dout[2] = OUTPUT(E1_r16s[2]);


--dout[1] is dout[1]
--operation mode is output

dout[1] = OUTPUT(E1_r16s[1]);


--dout[0] is dout[0]
--operation mode is output

dout[0] = OUTPUT(E1_r16s[0]);