sreg8b.tan.rpt

用VHDL语言仿真乘法器设计。能够实现一般乘法运算。

; N/A           ; None        ; -0.967 ns ; b[3]  ; reg16b:inst3|r16s[12] ; clk      ;
; N/A           ; None        ; -0.967 ns ; b[3]  ; reg16b:inst3|r16s[13] ; clk      ;
; N/A           ; None        ; -1.011 ns ; b[5]  ; reg16b:inst3|r16s[13] ; clk      ;
; N/A           ; None        ; -1.042 ns ; b[6]  ; reg16b:inst3|r16s[14] ; clk      ;
; N/A           ; None        ; -1.071 ns ; b[5]  ; reg16b:inst3|r16s[14] ; clk      ;
; N/A           ; None        ; -1.091 ns ; b[4]  ; reg16b:inst3|r16s[15] ; clk      ;
; N/A           ; None        ; -1.091 ns ; b[4]  ; reg16b:inst3|r16s[14] ; clk      ;
; N/A           ; None        ; -1.091 ns ; b[4]  ; reg16b:inst3|r16s[12] ; clk      ;
; N/A           ; None        ; -1.091 ns ; b[4]  ; reg16b:inst3|r16s[13] ; clk      ;
; N/A           ; None        ; -1.102 ns ; b[6]  ; reg16b:inst3|r16s[15] ; clk      ;
; N/A           ; None        ; -1.105 ns ; b[1]  ; reg16b:inst3|r16s[15] ; clk      ;
; N/A           ; None        ; -1.105 ns ; b[1]  ; reg16b:inst3|r16s[14] ; clk      ;
; N/A           ; None        ; -1.105 ns ; b[1]  ; reg16b:inst3|r16s[12] ; clk      ;
; N/A           ; None        ; -1.105 ns ; b[1]  ; reg16b:inst3|r16s[13] ; clk      ;
; N/A           ; None        ; -1.131 ns ; b[5]  ; reg16b:inst3|r16s[15] ; clk      ;
+---------------+-------------+-----------+-------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 31 11:29:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sreg8b -c sreg8b --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "arictl:inst2|clkout" as buffer
Info: Clock "clk" has Internal fmax of 337.72 MHz between source register "sreg8b:inst4|reg8[0]" and destination register "reg16b:inst3|r16s[13]" (period= 2.961 ns)
    Info: + Longest register to register delay is 2.759 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y10_N7; Fanout = 8; REG Node = 'sreg8b:inst4|reg8[0]'
        Info: 2: + IC(0.572 ns) + CELL(0.454 ns) = 1.026 ns; Loc. = LC_X21_Y10_N9; Fanout = 3; COMB Node = 'andarith:inst1|dout[0]~87'
        Info: 3: + IC(0.336 ns) + CELL(0.434 ns) = 1.796 ns; Loc. = LC_X21_Y10_N0; Fanout = 2; COMB Node = 'reg16b:inst3|r16s[7]~110'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 1.856 ns; Loc. = LC_X21_Y10_N1; Fanout = 2; COMB Node = 'reg16b:inst3|r16s[8]~106'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.916 ns; Loc. = LC_X21_Y10_N2; Fanout = 2; COMB Node = 'reg16b:inst3|r16s[9]~102'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 1.976 ns; Loc. = LC_X21_Y10_N3; Fanout = 2; COMB Node = 'reg16b:inst3|r16s[10]~98'
        Info: 7: + IC(0.000 ns) + CELL(0.137 ns) = 2.113 ns; Loc. = LC_X21_Y10_N4; Fanout = 4; COMB Node = 'reg16b:inst3|r16s[11]~94'
        Info: 8: + IC(0.000 ns) + CELL(0.646 ns) = 2.759 ns; Loc. = LC_X21_Y10_N6; Fanout = 4; REG Node = 'reg16b:inst3|r16s[13]'
        Info: Total cell delay = 1.851 ns ( 67.09 % )
        Info: Total interconnect delay = 0.908 ns ( 32.91 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.143 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'
            Info: 2: + IC(0.425 ns) + CELL(0.720 ns) = 2.275 ns; Loc. = LC_X6_Y5_N8; Fanout = 24; REG Node = 'arictl:inst2|clkout'
            Info: 3: + IC(3.321 ns) + CELL(0.547 ns) = 6.143 ns; Loc. = LC_X21_Y10_N6; Fanout = 4; REG Node = 'reg16b:inst3|r16s[13]'
            Info: Total cell delay = 2.397 ns ( 39.02 % )
            Info: Total interconnect delay = 3.746 ns ( 60.98 % )
        Info: - Longest clock path from clock "clk" to source register is 6.143 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'
            Info: 2: + IC(0.425 ns) + CELL(0.720 ns) = 2.275 ns; Loc. = LC_X6_Y5_N8; Fanout = 24; REG Node = 'arictl:inst2|clkout'
            Info: 3: + IC(3.321 ns) + CELL(0.547 ns) = 6.143 ns; Loc. = LC_X22_Y10_N7; Fanout = 8; REG Node = 'sreg8b:inst4|reg8[0]'
            Info: Total cell delay = 2.397 ns ( 39.02 % )
            Info: Total interconnect delay = 3.746 ns ( 60.98 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "reg16b:inst3|r16s[15]" (data pin = "b[5]", clock pin = "clk") is 1.186 ns
    Info: + Longest pin to register delay is 7.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_109; Fanout = 1; PIN Node = 'b[5]'
        Info: 2: + IC(4.135 ns) + CELL(0.454 ns) = 5.724 ns; Loc. = LC_X22_Y10_N9; Fanout = 3; COMB Node = 'andarith:inst1|dout[5]~82'
        Info: 3: + IC(0.513 ns) + CELL(0.333 ns) = 6.570 ns; Loc. = LC_X21_Y10_N5; Fanout = 2; COMB Node = 'reg16b:inst3|r16s[12]~90COUT1_124'
        Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 6.632 ns; Loc. = LC_X21_Y10_N6; Fanout = 2; COMB Node = 'reg16b:inst3|r16s[13]~86COUT1_125'
        Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 6.694 ns; Loc. = LC_X21_Y10_N7; Fanout = 1; COMB Node = 'reg16b:inst3|r16s[14]~82COUT1_126'
        Info: 6: + IC(0.000 ns) + CELL(0.606 ns) = 7.300 ns; Loc. = LC_X21_Y10_N8; Fanout = 4; REG Node = 'reg16b:inst3|r16s[15]'
        Info: Total cell delay = 2.652 ns ( 36.33 % )
        Info: Total interconnect delay = 4.648 ns ( 63.67 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clk" to destination register is 6.143 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(0.425 ns) + CELL(0.720 ns) = 2.275 ns; Loc. = LC_X6_Y5_N8; Fanout = 24; REG Node = 'arictl:inst2|clkout'
        Info: 3: + IC(3.321 ns) + CELL(0.547 ns) = 6.143 ns; Loc. = LC_X21_Y10_N8; Fanout = 4; REG Node = 'reg16b:inst3|r16s[15]'
        Info: Total cell delay = 2.397 ns ( 39.02 % )
        Info: Total interconnect delay = 3.746 ns ( 60.98 % )
Info: tco from clock "clk" to destination pin "dout[7]" through register "reg16b:inst3|r16s[7]" is 10.210 ns
    Info: + Longest clock path from clock "clk" to source register is 6.143 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(0.425 ns) + CELL(0.720 ns) = 2.275 ns; Loc. = LC_X6_Y5_N8; Fanout = 24; REG Node = 'arictl:inst2|clkout'
        Info: 3: + IC(3.321 ns) + CELL(0.547 ns) = 6.143 ns; Loc. = LC_X21_Y10_N0; Fanout = 2; REG Node = 'reg16b:inst3|r16s[7]'
        Info: Total cell delay = 2.397 ns ( 39.02 % )
        Info: Total interconnect delay = 3.746 ns ( 60.98 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.894 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y10_N0; Fanout = 2; REG Node = 'reg16b:inst3|r16s[7]'
        Info: 2: + IC(2.272 ns) + CELL(1.622 ns) = 3.894 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'dout[7]'
        Info: Total cell delay = 1.622 ns ( 41.65 % )
        Info: Total interconnect delay = 2.272 ns ( 58.35 % )
Info: th for register "sreg8b:inst4|reg8[3]" (data pin = "start", clock pin = "clk") is 3.699 ns
    Info: + Longest clock path from clock "clk" to destination register is 6.103 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(0.425 ns) + CELL(0.720 ns) = 2.275 ns; Loc. = LC_X6_Y5_N8; Fanout = 24; REG Node = 'arictl:inst2|clkout'
        Info: 3: + IC(3.281 ns) + CELL(0.547 ns) = 6.103 ns; Loc. = LC_X9_Y2_N2; Fanout = 1; REG Node = 'sreg8b:inst4|reg8[3]'
        Info: Total cell delay = 2.397 ns ( 39.28 % )
        Info: Total interconnect delay = 3.706 ns ( 60.72 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 2.416 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_16; Fanout = 29; PIN Node = 'start'
        Info: 2: + IC(0.918 ns) + CELL(0.368 ns) = 2.416 ns; Loc. = LC_X9_Y2_N2; Fanout = 1; REG Node = 'sreg8b:inst4|reg8[3]'
        Info: Total cell delay = 1.498 ns ( 62.00 % )
        Info: Total interconnect delay = 0.918 ns ( 38.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Dec 31 11:29:45 2007
    Info: Elapsed time: 00:00:01