function.tan.rpt

来自「利用图元实现层次化设计,编程完成数字序列的乘积求和」· RPT 代码 · 共 275 行 · 第 1/5 页

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C5T144C6        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                             ; To                                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------+--------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 401.12 MHz ( period = 2.493 ns )                    ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[0]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[15] ; clk        ; clk      ; None                        ; None                      ; 2.279 ns                ;
; N/A                                     ; 410.34 MHz ( period = 2.437 ns )                    ; logic_control:inst|counter[4]                    ; logic_control:inst|clr                           ; clk        ; clk      ; None                        ; None                      ; 2.223 ns                ;
; N/A                                     ; 412.88 MHz ( period = 2.422 ns )                    ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[1]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[15] ; clk        ; clk      ; None                        ; None                      ; 2.208 ns                ;
; N/A                                     ; 412.88 MHz ( period = 2.422 ns )                    ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[0]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[14] ; clk        ; clk      ; None                        ; None                      ; 2.208 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[1]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[14] ; clk        ; clk      ; None                        ; None                      ; 2.137 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[0]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[13] ; clk        ; clk      ; None                        ; None                      ; 2.137 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[2]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[15] ; clk        ; clk      ; None                        ; None                      ; 2.133 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[3]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[15] ; clk        ; clk      ; None                        ; None                      ; 2.102 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; logic_control:inst|counter[3]                    ; logic_control:inst|counter[5]                    ; clk        ; clk      ; None                        ; None                      ; 2.091 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; logic_control:inst|counter[3]                    ; logic_control:inst|clr                           ; clk        ; clk      ; None                        ; None                      ; 2.086 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[1]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[13] ; clk        ; clk      ; None                        ; None                      ; 2.066 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[0]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[12] ; clk        ; clk      ; None                        ; None                      ; 2.066 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; logic_control:inst|counter[0]                    ; logic_control:inst|clr                           ; clk        ; clk      ; None                        ; None                      ; 2.063 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[2]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[14] ; clk        ; clk      ; None                        ; None                      ; 2.062 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; logic_control:inst|counter[2]                    ; logic_control:inst|clr                           ; clk        ; clk      ; None                        ; None                      ; 2.040 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[3]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[14] ; clk        ; clk      ; None                        ; None                      ; 2.031 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[4]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[15] ; clk        ; clk      ; None                        ; None                      ; 1.999 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[1]  ; lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[12] ; clk        ; clk      ; None                        ; None                      ; 1.995 ns                ;