function.fnsim.qmsg

利用图元实现层次化设计,编程完成数字序列的乘积求和

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ff lpm_dff5:inst10\|lpm_ff:lpm_ff_component " "Info: Elaborating entity \"lpm_ff\" for hierarchy \"lpm_dff5:inst10\|lpm_ff:lpm_ff_component\"" {  } { { "lpm_dff5.vhd" "lpm_ff_component" { Text "E:/function2/lpm_dff5.vhd" 73 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_dff5:inst10\|lpm_ff:lpm_ff_component " "Info: Elaborated megafunction instantiation \"lpm_dff5:inst10\|lpm_ff:lpm_ff_component\"" {  } { { "lpm_dff5.vhd" "" { Text "E:/function2/lpm_dff5.vhd" 73 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_add_sub0.vhd 2 1 " "Warning: Using design file lpm_add_sub0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_add_sub0-SYN " "Info: Found design unit 1: lpm_add_sub0-SYN" {  } { { "lpm_add_sub0.vhd" "" { Text "E:/function2/lpm_add_sub0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub0 " "Info: Found entity 1: lpm_add_sub0" {  } { { "lpm_add_sub0.vhd" "" { Text "E:/function2/lpm_add_sub0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub0 lpm_add_sub0:inst11 " "Info: Elaborating entity \"lpm_add_sub0\" for hierarchy \"lpm_add_sub0:inst11\"" {  } { { "Block1.bdf" "inst11" { Schematic "E:/function2/Block1.bdf" { { 136 448 608 232 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_add_sub0:inst11\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_add_sub0:inst11\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub0.vhd" "lpm_add_sub_component" { Text "E:/function2/lpm_add_sub0.vhd" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub0:inst11\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"lpm_add_sub0:inst11\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_sub0.vhd" "" { Text "E:/function2/lpm_add_sub0.vhd" 72 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_2pe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_2pe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_2pe " "Info: Found entity 1: add_sub_2pe" {  } { { "db/add_sub_2pe.tdf" "" { Text "E:/function2/db/add_sub_2pe.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_2pe lpm_add_sub0:inst11\|lpm_add_sub:lpm_add_sub_component\|add_sub_2pe:auto_generated " "Info: Elaborating entity \"add_sub_2pe\" for hierarchy \"lpm_add_sub0:inst11\|lpm_add_sub:lpm_add_sub_component\|add_sub_2pe:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 117 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_mult0.vhd 2 1 " "Warning: Using design file lpm_mult0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_mult0-SYN " "Info: Found design unit 1: lpm_mult0-SYN" {  } { { "lpm_mult0.vhd" "" { Text "E:/function2/lpm_mult0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult0 " "Info: Found entity 1: lpm_mult0" {  } { { "lpm_mult0.vhd" "" { Text "E:/function2/lpm_mult0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult0 lpm_mult0:inst1 " "Info: Elaborating entity \"lpm_mult0\" for hierarchy \"lpm_mult0:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "E:/function2/Block1.bdf" { { 120 256 424 216 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult lpm_mult0:inst1\|lpm_mult:lpm_mult_component " "Info: Elaborating entity \"lpm_mult\" for hierarchy \"lpm_mult0:inst1\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult0.vhd" "lpm_mult_component" { Text "E:/function2/lpm_mult0.vhd" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult0:inst1\|lpm_mult:lpm_mult_component " "Info: Elaborated megafunction instantiation \"lpm_mult0:inst1\|lpm_mult:lpm_mult_component\"" {  } { { "lpm_mult0.vhd" "" { Text "E:/function2/lpm_mult0.vhd" 75 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_jeo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_jeo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_jeo " "Info: Found entity 1: mult_jeo" {  } { { "db/mult_jeo.tdf" "" { Text "E:/function2/db/mult_jeo.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_jeo lpm_mult0:inst1\|lpm_mult:lpm_mult_component\|mult_jeo:auto_generated " "Info: Elaborating entity \"mult_jeo\" for hierarchy \"lpm_mult0:inst1\|lpm_mult:lpm_mult_component\|mult_jeo:auto_generated\"" {  } { { "lpm_mult.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf" 372 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rightshift:inst12\|Dout\[12\] data_in GND " "Warning: Reduced register \"rightshift:inst12\|Dout\[12\]\" with stuck data_in port to stuck value GND" {  } { { "rightshift.vhd" "" { Text "E:/function2/rightshift.vhd" 17 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rightshift:inst12\|Dout\[13\] data_in GND " "Warning: Reduced register \"rightshift:inst12\|Dout\[13\]\" with stuck data_in port to stuck value GND" {  } { { "rightshift.vhd" "" { Text "E:/function2/rightshift.vhd" 17 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rightshift:inst12\|Dout\[14\] data_in GND " "Warning: Reduced register \"rightshift:inst12\|Dout\[14\]\" with stuck data_in port to stuck value GND" {  } { { "rightshift.vhd" "" { Text "E:/function2/rightshift.vhd" 17 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rightshift:inst12\|Dout\[15\] data_in GND " "Warning: Reduced register \"rightshift:inst12\|Dout\[15\]\" with stuck data_in port to stuck value GND" {  } { { "rightshift.vhd" "" { Text "E:/function2/rightshift.vhd" 17 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 42 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 42 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 02 09:30:11 2009 " "Info: Processing ended: Thu Apr 02 09:30:11 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}