function.fnsim.qmsg

利用图元实现层次化设计,编程完成数字序列的乘积求和

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 02 09:30:09 2009 " "Info: Processing started: Thu Apr 02 09:30:09 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off function -c function --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off function -c function --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rightshift.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rightshift.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rightshift-beha " "Info: Found design unit 1: rightshift-beha" {  } { { "rightshift.vhd" "" { Text "E:/function2/rightshift.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rightshift " "Info: Found entity 1: rightshift" {  } { { "rightshift.vhd" "" { Text "E:/function2/rightshift.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "logic_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file logic_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 logic_control-beha " "Info: Found design unit 1: logic_control-beha" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 logic_control " "Info: Found entity 1: logic_control" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/function2/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "logic_control logic_control:inst " "Info: Elaborating entity \"logic_control\" for hierarchy \"logic_control:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "E:/function2/Block1.bdf" { { 8 256 352 104 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(20) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(20): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(23) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(23): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(27) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(27): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(30) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(30): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(33) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(33): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(36) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(36): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 36 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(39) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(39): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 39 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(42) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(42): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 42 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(45) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(45): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 45 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(48) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(48): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 48 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(52) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(52): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(55) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(55): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 55 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(58) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(58): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 58 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(61) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(61): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 61 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counter logic_control.vhd(64) " "Warning (10492): VHDL Process Statement warning at logic_control.vhd(64): signal \"counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "logic_control.vhd" "" { Text "E:/function2/logic_control.vhd" 64 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}