function.map.rpt

利用图元实现层次化设计,编程完成数字序列的乘积求和

; LPM_WIDTHR                                     ; 0          ; Untyped                    ;
; LPM_WIDTHS                                     ; 1          ; Integer                    ;
; LPM_REPRESENTATION                             ; UNSIGNED   ; Untyped                    ;
; LPM_PIPELINE                                   ; 0          ; Untyped                    ;
; LATENCY                                        ; 0          ; Untyped                    ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                    ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                    ;
; USE_EAB                                        ; OFF        ; Untyped                    ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped                    ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                    ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                    ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K        ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped                    ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                    ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                    ;
; CBXI_PARAMETER                                 ; mult_jeo   ; Untyped                    ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                    ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                    ;
+------------------------------------------------+------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                                      ;
+---------------------------------------+---------------------------------------------+
; Name                                  ; Value                                       ;
+---------------------------------------+---------------------------------------------+
; Number of entity instances            ; 1                                           ;
; Entity Instance                       ; lpm_mult0:inst1|lpm_mult:lpm_mult_component ;
;     -- LPM_WIDTHA                     ; 8                                           ;
;     -- LPM_WIDTHB                     ; 8                                           ;
;     -- LPM_WIDTHP                     ; 16                                          ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                                    ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                          ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                          ;
;     -- USE_EAB                        ; OFF                                         ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                        ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                          ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                          ;
+---------------------------------------+---------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Apr 02 09:22:27 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off function -c function
Info: Found 2 design units, including 1 entities, in source file rightshift.vhd
    Info: Found design unit 1: rightshift-beha
    Info: Found entity 1: rightshift
Info: Found 2 design units, including 1 entities, in source file logic_control.vhd
    Info: Found design unit 1: logic_control-beha
    Info: Found entity 1: logic_control
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Info: Elaborating entity "logic_control" for hierarchy "logic_control:inst"
Warning (10492): VHDL Process Statement warning at logic_control.vhd(20): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(23): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(27): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(30): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(33): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(36): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(39): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(42): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(45): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(48): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(52): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(55): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(58): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(61): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(64): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(67): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(70): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(74): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(77): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(80): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(83): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(86): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(89): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(92): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(95): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(98): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(101): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(104): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(107): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(110): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(113): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(116): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(119): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(122): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at logic_control.vhd(125): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "rightshift" for hierarchy "rightshift:inst12"
Warning: Using design file lpm_dff5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_dff5-SYN
    Info: Found entity 1: lpm_dff5
Info: Elaborating entity "lpm_dff5" for hierarchy "lpm_dff5:inst10"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Elaborating entity "lpm_ff" for hierarchy "lpm_dff5:inst10|lpm_ff:lpm_ff_component"
Info: Elaborated megafunction instantiation "lpm_dff5:inst10|lpm_ff:lpm_ff_component"
Warning: Using design file lpm_add_sub0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_add_sub0-SYN
    Info: Found entity 1: lpm_add_sub0
Info: Elaborating entity "lpm_add_sub0" for hierarchy "lpm_add_sub0:inst11"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "lpm_add_sub0:inst11|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "lpm_add_sub0:inst11|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_2pe.tdf
    Info: Found entity 1: add_sub_2pe
Info: Elaborating entity "add_sub_2pe" for hierarchy "lpm_add_sub0:inst11|lpm_add_sub:lpm_add_sub_component|add_sub_2pe:auto_generated"
Warning: Using design file lpm_mult0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_mult0-SYN
    Info: Found entity 1: lpm_mult0
Info: Elaborating entity "lpm_mult0" for hierarchy "lpm_mult0:inst1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "lpm_mult0:inst1|lpm_mult:lpm_mult_component"
Info: Elaborated megafunction instantiation "lpm_mult0:inst1|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_jeo.tdf
    Info: Found entity 1: mult_jeo
Info: Elaborating entity "mult_jeo" for hierarchy "lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated"
Warning: Reduced register "rightshift:inst12|Dout[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "rightshift:inst12|Dout[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "rightshift:inst12|Dout[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "rightshift:inst12|Dout[15]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "q[15]" stuck at GND
    Warning: Pin "q[14]" stuck at GND
    Warning: Pin "q[13]" stuck at GND
    Warning: Pin "q[12]" stuck at GND
Info: Implemented 87 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 19 output pins
    Info: Implemented 49 logic cells
    Info: Implemented 1 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings
    Info: Processing ended: Thu Apr 02 09:22:30 2009
    Info: Elapsed time: 00:00:03