logic_control.vhd

利用图元实现层次化设计,编程完成数字序列的乘积求和

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity logic_control is 
	port(
		clk,start:        in std_logic;
		clr,addclk,OE:  out std_logic);
end entity logic_control;

architecture beha of logic_control is
signal counter:  std_logic_vector(5 downto 0);
begin

process(clk,start)
		begin
		if(rising_edge(clk) and start='1') then
		   counter<="000001";
		elsif(rising_edge(clk)and counter="000001") then--计数开始,清零
		   clr<='1';
		   counter<="000010";
		elsif(rising_edge(clk)and counter="000010") then--加法时钟1
		   clr<='0';
		   addclk<='1';
		   counter<="000011";
		elsif(rising_edge(clk)and counter="000011") then
		   addclk<='0';
		   counter<="000100";
		elsif(rising_edge(clk)and counter="000100") then--加法时钟2
		   addclk<='1';
		   counter<="000101";
		elsif(rising_edge(clk)and counter="000101") then
		   addclk<='0';
		   counter<="000110";
		elsif(rising_edge(clk)and counter="000110") then--加法时钟3
		   addclk<='1';
		   counter<="000111";
		elsif( rising_edge(clk)and counter="000111") then
		    addclk<='0';
		   counter<="001000";
		elsif(rising_edge(clk)and counter="001000") then--加法时钟4
		    addclk<='1';
		   counter<="001001";
		elsif(rising_edge(clk)and counter="001001") then
		   addclk<='0';
		   counter<="001010";
		elsif(rising_edge(clk)and counter="001010") then--加法时钟5
		   clr<='0';
		   addclk<='1';
		   counter<="001011";
		elsif(rising_edge(clk)and counter="001011") then
		   addclk<='0';
		   counter<="001100";
		elsif(rising_edge(clk)and counter="001100") then--加法时钟6
		   addclk<='1';
		   counter<="001101";
		elsif(rising_edge(clk)and counter="001101") then
		   addclk<='0';
		   counter<="001110";
		elsif(rising_edge(clk)and counter="001110") then--加法时钟7
		   addclk<='1';
		   counter<="001111";
		elsif( rising_edge(clk)and counter="001111") then
		   addclk<='0';
		   counter<="010000";
		elsif(rising_edge(clk)and counter="010000") then--加法时钟8
		   addclk<='1';
		   counter<="010001";
		elsif(rising_edge(clk)and counter="010001") then
		   addclk<='0';
		   counter<="010010";

		elsif(rising_edge(clk)and counter="010010") then--加法时钟9
		   addclk<='1';
		   counter<="010011";
		elsif(rising_edge(clk)and counter="010011") then
		   addclk<='0';
		   counter<="010100";
		elsif(rising_edge(clk)and counter="010100") then--加法时钟10
		   addclk<='1';
		   counter<="010101";
		elsif(rising_edge(clk)and counter="010101") then
		   addclk<='0';
		   counter<="010110";
		elsif(rising_edge(clk)and counter="010110") then--加法时钟11
		   addclk<='1';
		   counter<="010111";
		elsif(rising_edge(clk)and counter="010111") then
		   addclk<='0';
		   counter<="011000";
		elsif(rising_edge(clk)and counter="011000") then--加法时钟12
		   addclk<='1';
		   counter<="011001";
		elsif(rising_edge(clk)and counter="011001") then
		   addclk<='0';
		   counter<="011010";
		elsif(rising_edge(clk)and counter="011010") then--加法时钟13
		   addclk<='1';
		   counter<="011011";
		elsif(rising_edge(clk)and counter="011011") then
		   addclk<='0';
		   counter<="011100";
		elsif(rising_edge(clk)and counter="011100") then--加法时钟14
		   addclk<='1';
		   counter<="011101";
		elsif(rising_edge(clk)and counter="011101") then
		   addclk<='0';
		   counter<="011110";
		elsif(rising_edge(clk)and counter="011110") then--加法时钟15
		   addclk<='1';
		   counter<="011111";
		elsif(rising_edge(clk)and counter="011111") then
		   addclk<='0';
		   counter<="100000";
		elsif(rising_edge(clk)and counter="100000") then--加法时钟16
		   addclk<='1';
		   counter<="100001";
		elsif(rising_edge(clk)and counter="100001") then
		   addclk<='0';
		   counter<="100010";
		elsif(rising_edge(clk)and counter="100010") then--输出使能
		   OE<='1';
		   counter<="000000";
		elsif(rising_edge(clk)and counter="000000") then--计数停止
		   OE<='0';
		   clr<='0';
		   addclk<='0';
	    end if;
end process;

end beha;