function.sim.rpt

利用图元实现层次化设计,编程完成数字序列的乘积求和

; Detect glitches                                                                            ; Off          ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off          ; Off           ;
; Generate Signal Activity File                                                              ; Off          ; Off           ;
; Group bus channels in simulation results                                                   ; Off          ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On           ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE   ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off          ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off          ;               ;
; Glitch Filtering                                                                           ; Off          ; Off           ;
+--------------------------------------------------------------------------------------------+--------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      77.66 % ;
; Total nodes checked                                 ; 449          ;
; Total output ports checked                          ; 479          ;
; Total output ports with complete 1/0-value coverage ; 372          ;
; Total output ports with no 1/0-value coverage       ; 99           ;
; Total output ports with no 1-value coverage         ; 99           ;
; Total output ports with no 0-value coverage         ; 107          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                     ;
+----------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                ; Output Port Name                                                                                                  ; Output Port Type ;
+----------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+------------------+
; |Block1|clr                                                                                              ; |Block1|clr                                                                                                       ; pin_out          ;
; |Block1|clk                                                                                              ; |Block1|clk                                                                                                       ; out              ;
; |Block1|start                                                                                            ; |Block1|start                                                                                                     ; out              ;
; |Block1|addclk                                                                                           ; |Block1|addclk                                                                                                    ; pin_out          ;
; |Block1|OE                                                                                               ; |Block1|OE                                                                                                        ; pin_out          ;
; |Block1|xa[5]                                                                                            ; |Block1|xa[5]                                                                                                     ; out              ;
; |Block1|xa[4]                                                                                            ; |Block1|xa[4]                                                                                                     ; out              ;
; |Block1|xa[3]                                                                                            ; |Block1|xa[3]                                                                                                     ; out              ;
; |Block1|xa[2]                                                                                            ; |Block1|xa[2]                                                                                                     ; out              ;
; |Block1|xa[1]                                                                                            ; |Block1|xa[1]                                                                                                     ; out              ;
; |Block1|xa[0]                                                                                            ; |Block1|xa[0]                                                                                                     ; out              ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1 ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1~DATAOUT2 ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1 ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1~DATAOUT3 ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1 ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1~DATAOUT4 ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1 ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1~DATAOUT5 ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1 ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1~DATAOUT6 ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1 ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_mult:mac_mult1~DATAOUT7 ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2   ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2~DATAOUT2   ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2   ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2~DATAOUT3   ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2   ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2~DATAOUT4   ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2   ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2~DATAOUT5   ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2   ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2~DATAOUT6   ; dataout          ;
; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2   ; |Block1|lpm_mult0:inst1|lpm_mult:lpm_mult_component|mult_jeo:auto_generated|cycloneii_mac_out:mac_out2~DATAOUT7   ; dataout          ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[9]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[9]                                                           ; out              ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                           ; out              ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[7]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[7]                                                           ; out              ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                           ; out              ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[5]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[5]                                                           ; out              ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[4]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[4]                                                           ; out              ;
; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                  ; |Block1|lpm_dff5:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                           ; out              ;