shift_taps_93m.tdf

采用加法树流水线乘法构造八位乘法器

--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" NUMBER_OF_TAPS=1 TAP_DISTANCE=17 WIDTH=10 clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 6.0 cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altshift_taps 2006:01:26:13:08:24:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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FUNCTION altsyncram_ec81 (address_a[3..0], address_b[3..0], clock0, clocken0, data_a[9..0], wren_a)
RETURNS ( q_b[9..0]);
FUNCTION cntr_7oc (clk_en, clock)
RETURNS ( q[3..0]);

--synthesis_resources = lut 7 M4K 10 reg 4 
SUBDESIGN shift_taps_93m
( 
	clock	:	input;
	shiftin[9..0]	:	input;
	shiftout[9..0]	:	output;
	taps[9..0]	:	output;
) 
VARIABLE 
	altsyncram2 : altsyncram_ec81;
	cntr1 : cntr_7oc;
	clken	: NODE;

BEGIN 
	altsyncram2.address_a[] = cntr1.q[];
	altsyncram2.address_b[] = cntr1.q[];
	altsyncram2.clock0 = clock;
	altsyncram2.clocken0 = clken;
	altsyncram2.data_a[] = ( shiftin[]);
	altsyncram2.wren_a = B"1";
	cntr1.clk_en = clken;
	cntr1.clock = clock;
	clken = VCC;
	shiftout[9..0] = altsyncram2.q_b[9..0];
	taps[] = altsyncram2.q_b[];
END;
--VALID FILE