adder.map.summary

采用加法树流水线乘法构造八位乘法器

Analysis & Synthesis Status : Successful - Thu Apr 02 14:08:48 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : adder
Top-level Entity Name : add
Family : Cyclone II
Total logic elements : 289
Total registers : 289
Total pins : 34
Total virtual pins : 0
Total memory bits : 821
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0