adder.tan.rpt

来自「采用加法树流水线乘法构造八位乘法器」· RPT 代码 · 共 212 行 · 第 1/5 页

+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 5.820 ns                                       ; xb[6]                                                                                                                             ; adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|ram_block3a0~porta_datain_reg1 ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.863 ns                                       ; adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2|q_b[0]                         ; mult[11]                                                                                                                          ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.106 ns                                      ; xa[0]                                                                                                                             ; tran8to9:inst|b[1]                                                                                                                ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 235.07 MHz ( period = 4.254 ns ) ; adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|ram_block3a0~portb_address_reg1 ; adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2|q_b[7]                          ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                                   ;                                                                                                                                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+