tran10to12.vhd

来自「采用加法树流水线乘法构造八位乘法器」· VHDL 代码 · 共 26 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity tran10to12 is 
	port(
		a10,b10:		in std_logic_vector(9 downto 0);
		clk:        in std_logic;
		a12,b12:		out std_logic_vector(11 downto 0));
end entity tran10to12;

architecture beha of tran10to12 is
signal  a,b:std_logic_vector(11 downto 0);
begin
a12<=a;
b12<=b;
process(clk)
		begin	
		if(rising_edge(clk)) then
	           a<="00"&a10;
	           b<=b10&"00";
	end if;
end process;
end beha;