adder.map.eqn

采用加法树流水线乘法构造八位乘法器

reg4[1]_lut_out = reg3[1];
reg4[1] = DFFEA(reg4[1]_lut_out, clk, !rst, , , , );


--reg4[0] is reg4[0]
--operation mode is normal

reg4[0]_lut_out = reg3[0];
reg4[0] = DFFEA(reg4[0]_lut_out, clk, !rst, , , , );


--reg2[12] is reg2[12]
--operation mode is normal

reg2[12]_lut_out = reg1[13];
reg2[12] = DFFEA(reg2[12]_lut_out, clk, !rst, , , , );


--reg2[13] is reg2[13]
--operation mode is normal

reg2[13]_lut_out = reg1[14];
reg2[13] = DFFEA(reg2[13]_lut_out, clk, !rst, , , , );


--reg2[10] is reg2[10]
--operation mode is normal

reg2[10]_lut_out = reg1[11];
reg2[10] = DFFEA(reg2[10]_lut_out, clk, !rst, , , , );


--reg2[11] is reg2[11]
--operation mode is normal

reg2[11]_lut_out = reg1[12];
reg2[11] = DFFEA(reg2[11]_lut_out, clk, !rst, , , , );


--reg3[7] is reg3[7]
--operation mode is normal

reg3[7]_lut_out = reg2[8];
reg3[7] = DFFEA(reg3[7]_lut_out, clk, !rst, , , , );


--reg3[6] is reg3[6]
--operation mode is normal

reg3[6]_lut_out = reg2[7];
reg3[6] = DFFEA(reg3[6]_lut_out, clk, !rst, , , , );


--reg3[8] is reg3[8]
--operation mode is normal

reg3[8]_lut_out = reg2[9];
reg3[8] = DFFEA(reg3[8]_lut_out, clk, !rst, , , , );


--reg2[15] is reg2[15]
--operation mode is normal

reg2[15]_lut_out = reg1[16];
reg2[15] = DFFEA(reg2[15]_lut_out, clk, !rst, , , , );


--reg2[14] is reg2[14]
--operation mode is normal

reg2[14]_lut_out = reg1[15];
reg2[14] = DFFEA(reg2[14]_lut_out, clk, !rst, , , , );


--reg3[4] is reg3[4]
--operation mode is normal

reg3[4]_lut_out = reg2[5];
reg3[4] = DFFEA(reg3[4]_lut_out, clk, !rst, , , , );


--reg3[5] is reg3[5]
--operation mode is normal

reg3[5]_lut_out = reg2[6];
reg3[5] = DFFEA(reg3[5]_lut_out, clk, !rst, , , , );


--reg3[3] is reg3[3]
--operation mode is normal

reg3[3]_lut_out = reg2[2] & reg2[4] # reg2[3] # !reg2[2] & reg2[4] & reg2[3];
reg3[3] = DFFEA(reg3[3]_lut_out, clk, !rst, , , , );


--reg3[2] is reg3[2]
--operation mode is normal

reg3[2]_lut_out = reg2[2] $ reg2[4] $ reg2[3];
reg3[2] = DFFEA(reg3[2]_lut_out, clk, !rst, , , , );


--reg3[1] is reg3[1]
--operation mode is normal

reg3[1]_lut_out = reg2[1];
reg3[1] = DFFEA(reg3[1]_lut_out, clk, !rst, , , , );


--reg3[0] is reg3[0]
--operation mode is normal

reg3[0]_lut_out = reg2[0];
reg3[0] = DFFEA(reg3[0]_lut_out, clk, !rst, , , , );


--reg1[13] is reg1[13]
--operation mode is normal

reg1[13]_lut_out = b[6];
reg1[13] = DFFEA(reg1[13]_lut_out, clk, !rst, , , , );


--reg1[14] is reg1[14]
--operation mode is normal

reg1[14]_lut_out = a[7];
reg1[14] = DFFEA(reg1[14]_lut_out, clk, !rst, , , , );


--reg1[11] is reg1[11]
--operation mode is normal

reg1[11]_lut_out = b[5];
reg1[11] = DFFEA(reg1[11]_lut_out, clk, !rst, , , , );


--reg1[12] is reg1[12]
--operation mode is normal

reg1[12]_lut_out = a[6];
reg1[12] = DFFEA(reg1[12]_lut_out, clk, !rst, , , , );


--reg2[8] is reg2[8]
--operation mode is normal

reg2[8]_lut_out = reg1[9];
reg2[8] = DFFEA(reg2[8]_lut_out, clk, !rst, , , , );


--reg2[7] is reg2[7]
--operation mode is normal

reg2[7]_lut_out = reg1[8];
reg2[7] = DFFEA(reg2[7]_lut_out, clk, !rst, , , , );


--reg2[9] is reg2[9]
--operation mode is normal

reg2[9]_lut_out = reg1[10];
reg2[9] = DFFEA(reg2[9]_lut_out, clk, !rst, , , , );


--reg1[16] is reg1[16]
--operation mode is normal

reg1[16]_lut_out = a[8];
reg1[16] = DFFEA(reg1[16]_lut_out, clk, !rst, , , , );


--reg1[15] is reg1[15]
--operation mode is normal

reg1[15]_lut_out = b[7];
reg1[15] = DFFEA(reg1[15]_lut_out, clk, !rst, , , , );


--reg2[5] is reg2[5]
--operation mode is normal

reg2[5]_lut_out = reg1[6];
reg2[5] = DFFEA(reg2[5]_lut_out, clk, !rst, , , , );


--reg2[6] is reg2[6]
--operation mode is normal

reg2[6]_lut_out = reg1[7];
reg2[6] = DFFEA(reg2[6]_lut_out, clk, !rst, , , , );


--reg2[2] is reg2[2]
--operation mode is normal

reg2[2]_lut_out = reg1[1] & reg1[3] # reg1[2] # !reg1[1] & reg1[3] & reg1[2];
reg2[2] = DFFEA(reg2[2]_lut_out, clk, !rst, , , , );


--reg2[4] is reg2[4]
--operation mode is normal

reg2[4]_lut_out = reg1[5];
reg2[4] = DFFEA(reg2[4]_lut_out, clk, !rst, , , , );


--reg2[3] is reg2[3]
--operation mode is normal

reg2[3]_lut_out = reg1[4];
reg2[3] = DFFEA(reg2[3]_lut_out, clk, !rst, , , , );


--reg2[1] is reg2[1]
--operation mode is normal

reg2[1]_lut_out = reg1[1] $ reg1[3] $ reg1[2];
reg2[1] = DFFEA(reg2[1]_lut_out, clk, !rst, , , , );


--reg2[0] is reg2[0]
--operation mode is normal

reg2[0]_lut_out = reg1[0];
reg2[0] = DFFEA(reg2[0]_lut_out, clk, !rst, , , , );


--reg1[9] is reg1[9]
--operation mode is normal

reg1[9]_lut_out = b[4];
reg1[9] = DFFEA(reg1[9]_lut_out, clk, !rst, , , , );


--reg1[8] is reg1[8]
--operation mode is normal

reg1[8]_lut_out = a[4];
reg1[8] = DFFEA(reg1[8]_lut_out, clk, !rst, , , , );


--reg1[10] is reg1[10]
--operation mode is normal

reg1[10]_lut_out = a[5];
reg1[10] = DFFEA(reg1[10]_lut_out, clk, !rst, , , , );


--reg1[6] is reg1[6]
--operation mode is normal

reg1[6]_lut_out = a[3];
reg1[6] = DFFEA(reg1[6]_lut_out, clk, !rst, , , , );


--reg1[7] is reg1[7]
--operation mode is normal

reg1[7]_lut_out = b[3];
reg1[7] = DFFEA(reg1[7]_lut_out, clk, !rst, , , , );


--reg1[1] is reg1[1]
--operation mode is normal

reg1[1]_lut_out = a[0] & b[0];
reg1[1] = DFFEA(reg1[1]_lut_out, clk, !rst, , , , );


--reg1[3] is reg1[3]
--operation mode is normal

reg1[3]_lut_out = b[1];
reg1[3] = DFFEA(reg1[3]_lut_out, clk, !rst, , , , );


--reg1[2] is reg1[2]
--operation mode is normal

reg1[2]_lut_out = a[1];
reg1[2] = DFFEA(reg1[2]_lut_out, clk, !rst, , , , );


--reg1[5] is reg1[5]
--operation mode is normal

reg1[5]_lut_out = b[2];
reg1[5] = DFFEA(reg1[5]_lut_out, clk, !rst, , , , );


--reg1[4] is reg1[4]
--operation mode is normal

reg1[4]_lut_out = a[2];
reg1[4] = DFFEA(reg1[4]_lut_out, clk, !rst, , , , );


--reg1[0] is reg1[0]
--operation mode is normal

reg1[0]_lut_out = a[0] $ b[0];
reg1[0] = DFFEA(reg1[0]_lut_out, clk, !rst, , , , );


--A1L32 is c~54
--operation mode is normal

A1L32 = !rst;


--b[8] is b[8]
--operation mode is input

b[8] = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--b[6] is b[6]
--operation mode is input

b[6] = INPUT();


--a[7] is a[7]
--operation mode is input

a[7] = INPUT();


--b[5] is b[5]
--operation mode is input

b[5] = INPUT();


--a[6] is a[6]
--operation mode is input

a[6] = INPUT();


--a[8] is a[8]
--operation mode is input

a[8] = INPUT();


--b[7] is b[7]
--operation mode is input

b[7] = INPUT();


--b[4] is b[4]
--operation mode is input

b[4] = INPUT();


--a[4] is a[4]
--operation mode is input

a[4] = INPUT();


--a[5] is a[5]
--operation mode is input

a[5] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--sum[8] is sum[8]
--operation mode is output

sum[8] = OUTPUT(A1L651Q);


--sum[7] is sum[7]
--operation mode is output

sum[7] = OUTPUT(A1L451Q);


--sum[6] is sum[6]
--operation mode is output

sum[6] = OUTPUT(A1L251Q);


--sum[5] is sum[5]
--operation mode is output

sum[5] = OUTPUT(A1L051Q);


--sum[4] is sum[4]
--operation mode is output

sum[4] = OUTPUT(A1L841Q);


--sum[3] is sum[3]
--operation mode is output

sum[3] = OUTPUT(A1L641Q);


--sum[2] is sum[2]
--operation mode is output

sum[2] = OUTPUT(A1L441Q);


--sum[1] is sum[1]
--operation mode is output

sum[1] = OUTPUT(A1L241Q);


--sum[0] is sum[0]
--operation mode is output

sum[0] = OUTPUT(A1L041Q);


--c is c
--operation mode is output

c = OUTPUT(A1L42Q);