adder.map.eqn

采用加法树流水线乘法构造八位乘法器

--A1L651Q is sum[8]~reg0
--operation mode is normal

A1L651Q_lut_out = reg8[8] $ reg8[10] $ reg8[9];
A1L651Q = DFFEA(A1L651Q_lut_out, clk, !rst, , , , );


--A1L451Q is sum[7]~reg0
--operation mode is normal

A1L451Q_lut_out = reg8[7];
A1L451Q = DFFEA(A1L451Q_lut_out, clk, !rst, , , , );


--A1L251Q is sum[6]~reg0
--operation mode is normal

A1L251Q_lut_out = reg8[6];
A1L251Q = DFFEA(A1L251Q_lut_out, clk, !rst, , , , );


--A1L051Q is sum[5]~reg0
--operation mode is normal

A1L051Q_lut_out = reg8[5];
A1L051Q = DFFEA(A1L051Q_lut_out, clk, !rst, , , , );


--A1L841Q is sum[4]~reg0
--operation mode is normal

A1L841Q_lut_out = reg8[4];
A1L841Q = DFFEA(A1L841Q_lut_out, clk, !rst, , , , );


--A1L641Q is sum[3]~reg0
--operation mode is normal

A1L641Q_lut_out = reg8[3];
A1L641Q = DFFEA(A1L641Q_lut_out, clk, !rst, , , , );


--A1L441Q is sum[2]~reg0
--operation mode is normal

A1L441Q_lut_out = reg8[2];
A1L441Q = DFFEA(A1L441Q_lut_out, clk, !rst, , , , );


--A1L241Q is sum[1]~reg0
--operation mode is normal

A1L241Q_lut_out = reg8[1];
A1L241Q = DFFEA(A1L241Q_lut_out, clk, !rst, , , , );


--A1L041Q is sum[0]~reg0
--operation mode is normal

A1L041Q_lut_out = reg8[0];
A1L041Q = DFFEA(A1L041Q_lut_out, clk, !rst, , , , );


--A1L42Q is c~reg0
--operation mode is normal

A1L42Q_lut_out = reg8[9] & reg8[8] # reg8[10] # !reg8[9] & reg8[8] & reg8[10];
A1L42Q = DFFEA(A1L42Q_lut_out, clk, , , A1L32, , );


--reg8[8] is reg8[8]
--operation mode is normal

reg8[8]_lut_out = reg7[8] & reg7[9] # reg7[7] # !reg7[8] & reg7[9] & reg7[7];
reg8[8] = DFFEA(reg8[8]_lut_out, clk, !rst, , , , );


--reg8[10] is reg8[10]
--operation mode is normal

reg8[10]_lut_out = reg7[11];
reg8[10] = DFFEA(reg8[10]_lut_out, clk, !rst, , , , );


--reg8[9] is reg8[9]
--operation mode is normal

reg8[9]_lut_out = reg7[10];
reg8[9] = DFFEA(reg8[9]_lut_out, clk, !rst, , , , );


--reg8[7] is reg8[7]
--operation mode is normal

reg8[7]_lut_out = reg7[8] $ reg7[9] $ reg7[7];
reg8[7] = DFFEA(reg8[7]_lut_out, clk, !rst, , , , );


--reg8[6] is reg8[6]
--operation mode is normal

reg8[6]_lut_out = reg7[6];
reg8[6] = DFFEA(reg8[6]_lut_out, clk, !rst, , , , );


--reg8[5] is reg8[5]
--operation mode is normal

reg8[5]_lut_out = reg7[5];
reg8[5] = DFFEA(reg8[5]_lut_out, clk, !rst, , , , );


--reg8[4] is reg8[4]
--operation mode is normal

reg8[4]_lut_out = reg7[4];
reg8[4] = DFFEA(reg8[4]_lut_out, clk, !rst, , , , );


--reg8[3] is reg8[3]
--operation mode is normal

reg8[3]_lut_out = reg7[3];
reg8[3] = DFFEA(reg8[3]_lut_out, clk, !rst, , , , );


--reg8[2] is reg8[2]
--operation mode is normal

reg8[2]_lut_out = reg7[2];
reg8[2] = DFFEA(reg8[2]_lut_out, clk, !rst, , , , );


--reg8[1] is reg8[1]
--operation mode is normal

reg8[1]_lut_out = reg7[1];
reg8[1] = DFFEA(reg8[1]_lut_out, clk, !rst, , , , );


--reg8[0] is reg8[0]
--operation mode is normal

reg8[0]_lut_out = reg7[0];
reg8[0] = DFFEA(reg8[0]_lut_out, clk, !rst, , , , );


--reg7[8] is reg7[8]
--operation mode is normal

reg7[8]_lut_out = reg6[9];
reg7[8] = DFFEA(reg7[8]_lut_out, clk, !rst, , , , );


--reg7[9] is reg7[9]
--operation mode is normal

reg7[9]_lut_out = reg6[10];
reg7[9] = DFFEA(reg7[9]_lut_out, clk, !rst, , , , );


--reg7[7] is reg7[7]
--operation mode is normal

reg7[7]_lut_out = reg6[7] & reg6[8] # reg6[6] # !reg6[7] & reg6[8] & reg6[6];
reg7[7] = DFFEA(reg7[7]_lut_out, clk, !rst, , , , );


--reg7[11] is reg7[11]
--operation mode is normal

reg7[11]_lut_out = reg6[12];
reg7[11] = DFFEA(reg7[11]_lut_out, clk, !rst, , , , );


--reg7[10] is reg7[10]
--operation mode is normal

reg7[10]_lut_out = reg6[11];
reg7[10] = DFFEA(reg7[10]_lut_out, clk, !rst, , , , );


--reg7[6] is reg7[6]
--operation mode is normal

reg7[6]_lut_out = reg6[7] $ reg6[8] $ reg6[6];
reg7[6] = DFFEA(reg7[6]_lut_out, clk, !rst, , , , );


--reg7[5] is reg7[5]
--operation mode is normal

reg7[5]_lut_out = reg6[5];
reg7[5] = DFFEA(reg7[5]_lut_out, clk, !rst, , , , );


--reg7[4] is reg7[4]
--operation mode is normal

reg7[4]_lut_out = reg6[4];
reg7[4] = DFFEA(reg7[4]_lut_out, clk, !rst, , , , );


--reg7[3] is reg7[3]
--operation mode is normal

reg7[3]_lut_out = reg6[3];
reg7[3] = DFFEA(reg7[3]_lut_out, clk, !rst, , , , );


--reg7[2] is reg7[2]
--operation mode is normal

reg7[2]_lut_out = reg6[2];
reg7[2] = DFFEA(reg7[2]_lut_out, clk, !rst, , , , );


--reg7[1] is reg7[1]
--operation mode is normal

reg7[1]_lut_out = reg6[1];
reg7[1] = DFFEA(reg7[1]_lut_out, clk, !rst, , , , );


--reg7[0] is reg7[0]
--operation mode is normal

reg7[0]_lut_out = reg6[0];
reg7[0] = DFFEA(reg7[0]_lut_out, clk, !rst, , , , );


--reg6[9] is reg6[9]
--operation mode is normal

reg6[9]_lut_out = reg4[10];
reg6[9] = DFFEA(reg6[9]_lut_out, clk, !rst, , , , );


--reg6[10] is reg6[10]
--operation mode is normal

reg6[10]_lut_out = reg4[11];
reg6[10] = DFFEA(reg6[10]_lut_out, clk, !rst, , , , );


--reg6[7] is reg6[7]
--operation mode is normal

reg6[7]_lut_out = reg4[8];
reg6[7] = DFFEA(reg6[7]_lut_out, clk, !rst, , , , );


--reg6[8] is reg6[8]
--operation mode is normal

reg6[8]_lut_out = reg4[9];
reg6[8] = DFFEA(reg6[8]_lut_out, clk, !rst, , , , );


--reg6[6] is reg6[6]
--operation mode is normal

reg6[6]_lut_out = reg5[5] & reg5[6] # reg6[7] # !reg5[5] & reg5[6] & reg6[7];
reg6[6] = DFFEA(reg6[6]_lut_out, clk, !rst, , , , );


--reg6[12] is reg6[12]
--operation mode is normal

reg6[12]_lut_out = reg4[13];
reg6[12] = DFFEA(reg6[12]_lut_out, clk, !rst, , , , );


--reg6[11] is reg6[11]
--operation mode is normal

reg6[11]_lut_out = reg4[12];
reg6[11] = DFFEA(reg6[11]_lut_out, clk, !rst, , , , );


--reg6[5] is reg6[5]
--operation mode is normal

reg6[5]_lut_out = reg6[7] $ reg5[5] $ reg5[6];
reg6[5] = DFFEA(reg6[5]_lut_out, clk, !rst, , , , );


--reg6[4] is reg6[4]
--operation mode is normal

reg6[4]_lut_out = reg5[4];
reg6[4] = DFFEA(reg6[4]_lut_out, clk, !rst, , , , );


--reg6[3] is reg6[3]
--operation mode is normal

reg6[3]_lut_out = reg5[3];
reg6[3] = DFFEA(reg6[3]_lut_out, clk, !rst, , , , );


--reg6[2] is reg6[2]
--operation mode is normal

reg6[2]_lut_out = reg5[2];
reg6[2] = DFFEA(reg6[2]_lut_out, clk, !rst, , , , );


--reg6[1] is reg6[1]
--operation mode is normal

reg6[1]_lut_out = reg5[1];
reg6[1] = DFFEA(reg6[1]_lut_out, clk, !rst, , , , );


--reg6[0] is reg6[0]
--operation mode is normal

reg6[0]_lut_out = reg5[0];
reg6[0] = DFFEA(reg6[0]_lut_out, clk, !rst, , , , );


--reg4[10] is reg4[10]
--operation mode is normal

reg4[10]_lut_out = reg3[11];
reg4[10] = DFFEA(reg4[10]_lut_out, clk, !rst, , , , );


--reg4[11] is reg4[11]
--operation mode is normal

reg4[11]_lut_out = reg3[12];
reg4[11] = DFFEA(reg4[11]_lut_out, clk, !rst, , , , );


--reg4[8] is reg4[8]
--operation mode is normal

reg4[8]_lut_out = reg3[9];
reg4[8] = DFFEA(reg4[8]_lut_out, clk, !rst, , , , );


--reg4[9] is reg4[9]
--operation mode is normal

reg4[9]_lut_out = reg3[10];
reg4[9] = DFFEA(reg4[9]_lut_out, clk, !rst, , , , );


--reg5[5] is reg5[5]
--operation mode is normal

reg5[5]_lut_out = reg4[6] & reg4[5];
reg5[5] = DFFEA(reg5[5]_lut_out, clk, !rst, , , , );


--reg5[6] is reg5[6]
--operation mode is normal

reg5[6]_lut_out = reg4[7];
reg5[6] = DFFEA(reg5[6]_lut_out, clk, !rst, , , , );


--reg4[13] is reg4[13]
--operation mode is normal

reg4[13]_lut_out = reg3[14];
reg4[13] = DFFEA(reg4[13]_lut_out, clk, !rst, , , , );


--reg4[12] is reg4[12]
--operation mode is normal

reg4[12]_lut_out = reg3[13];
reg4[12] = DFFEA(reg4[12]_lut_out, clk, !rst, , , , );


--reg5[4] is reg5[4]
--operation mode is normal

reg5[4]_lut_out = reg4[6] $ reg4[5];
reg5[4] = DFFEA(reg5[4]_lut_out, clk, !rst, , , , );


--reg5[3] is reg5[3]
--operation mode is normal

reg5[3]_lut_out = reg4[3];
reg5[3] = DFFEA(reg5[3]_lut_out, clk, !rst, , , , );


--reg5[2] is reg5[2]
--operation mode is normal

reg5[2]_lut_out = reg4[2];
reg5[2] = DFFEA(reg5[2]_lut_out, clk, !rst, , , , );


--reg5[1] is reg5[1]
--operation mode is normal

reg5[1]_lut_out = reg4[1];
reg5[1] = DFFEA(reg5[1]_lut_out, clk, !rst, , , , );


--reg5[0] is reg5[0]
--operation mode is normal

reg5[0]_lut_out = reg4[0];
reg5[0] = DFFEA(reg5[0]_lut_out, clk, !rst, , , , );


--reg3[11] is reg3[11]
--operation mode is normal

reg3[11]_lut_out = reg2[12];
reg3[11] = DFFEA(reg3[11]_lut_out, clk, !rst, , , , );


--reg3[12] is reg3[12]
--operation mode is normal

reg3[12]_lut_out = reg2[13];
reg3[12] = DFFEA(reg3[12]_lut_out, clk, !rst, , , , );


--reg3[9] is reg3[9]
--operation mode is normal

reg3[9]_lut_out = reg2[10];
reg3[9] = DFFEA(reg3[9]_lut_out, clk, !rst, , , , );


--reg3[10] is reg3[10]
--operation mode is normal

reg3[10]_lut_out = reg2[11];
reg3[10] = DFFEA(reg3[10]_lut_out, clk, !rst, , , , );


--reg4[6] is reg4[6]
--operation mode is normal

reg4[6]_lut_out = reg3[7];
reg4[6] = DFFEA(reg4[6]_lut_out, clk, !rst, , , , );


--reg4[5] is reg4[5]
--operation mode is normal

reg4[5]_lut_out = reg3[6];
reg4[5] = DFFEA(reg4[5]_lut_out, clk, !rst, , , , );


--reg4[7] is reg4[7]
--operation mode is normal

reg4[7]_lut_out = reg3[8];
reg4[7] = DFFEA(reg4[7]_lut_out, clk, !rst, , , , );


--reg3[14] is reg3[14]
--operation mode is normal

reg3[14]_lut_out = reg2[15];
reg3[14] = DFFEA(reg3[14]_lut_out, clk, !rst, , , , );


--reg3[13] is reg3[13]
--operation mode is normal

reg3[13]_lut_out = reg2[14];
reg3[13] = DFFEA(reg3[13]_lut_out, clk, !rst, , , , );


--reg4[3] is reg4[3]
--operation mode is normal

reg4[3]_lut_out = reg3[4] & reg3[5] # reg3[3] # !reg3[4] & reg3[5] & reg3[3];
reg4[3] = DFFEA(reg4[3]_lut_out, clk, !rst, , , , );


--reg4[2] is reg4[2]
--operation mode is normal

reg4[2]_lut_out = reg3[2];
reg4[2] = DFFEA(reg4[2]_lut_out, clk, !rst, , , , );


--reg4[1] is reg4[1]
--operation mode is normal