adder.vhd

采用加法树流水线乘法构造八位乘法器

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity adder is 
	port(
		clk,rst:	in std_logic;
		a,b:		in std_logic_vector(15 downto 0);
		sum:		out std_logic_vector(15 downto 0));--带有最高位为进位
end entity adder;

architecture depict of adder is
	signal reg1:	std_logic_vector(31 downto 0);
	signal reg2:	std_logic_vector(30 downto 0);
	signal reg3:	std_logic_vector(29 downto 0);
	signal reg4:	std_logic_vector(28 downto 0);
	signal reg5:	std_logic_vector(27 downto 0);
	signal reg6:	std_logic_vector(26 downto 0);
	signal reg7:	std_logic_vector(25 downto 0);
	signal reg8:	std_logic_vector(24 downto 0);
	signal reg9:	std_logic_vector(23 downto 0);
	signal reg10:	std_logic_vector(22 downto 0);
	signal reg11:	std_logic_vector(21 downto 0);
	signal reg12:	std_logic_vector(20 downto 0);
	signal reg13:	std_logic_vector(19 downto 0);
	signal reg14:	std_logic_vector(18 downto 0);
	signal reg15:	std_logic_vector(17 downto 0);

begin
	bit0:process(clk,rst)
		begin
			if(rst = '1')then
				reg1 <= "00000000000000000000000000000000";
			elsif(rising_edge(clk))then		
				reg1(0) <= a(0) xor b(0);
				reg1(1) <= a(0) and b(0);
				reg1(2) <= a(1);
				reg1(3) <= b(1);
				reg1(4) <= a(2);
				reg1(5) <= b(2);
				reg1(6) <= a(3);
				reg1(7) <= b(3);
				reg1(8) <= a(4);
				reg1(9) <= b(4);
				reg1(10) <= a(5);
				reg1(11) <= b(5);
				reg1(12) <= a(6);
				reg1(13) <= b(6);
				reg1(14) <= a(7);
				reg1(15) <= b(7);
				reg1(16) <= a(8);
				reg1(17) <= b(8);
				reg1(18) <= a(9);
				reg1(19) <= b(9);
				reg1(20) <= a(10);
				reg1(21) <= b(10);
				reg1(22) <= a(11);
				reg1(23) <= b(11);
				reg1(24) <= a(12);
				reg1(25) <= b(12);
				reg1(26) <= a(13);
				reg1(27) <= b(13);
				reg1(28) <= a(14);
				reg1(29) <= b(14);
				reg1(30) <= a(15);
				reg1(31) <= b(15);
			end if;
	end process bit0;

	bit1:process(clk,rst)
		begin
			if(rst = '1') then
				reg2 <= "0000000000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg2(0) <= reg1(0);--第一次的结果
				reg2(1) <= reg1(1) xor reg1(2) xor reg1(3);--加法结果
				reg2(2) <= (reg1(1) and reg1(2)) or (reg1(1) and reg1(3)) or (reg1(2) and reg1(3));--进位结果
				reg2(30 downto 3) <= reg1(31 downto 4);
			end if;
	end process bit1;
	
	bit2:process(clk,rst)
		begin
			if(rst = '1') then
				reg3 <= "000000000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg3(1 downto 0) <= reg2(1 downto 0);--结果
				reg3(2) <= reg2(2) xor reg2(3) xor reg2(4);--加法结果
				reg3(3) <= (reg2(2) and reg2(3)) or (reg2(2) and reg2(4)) or (reg2(3) and reg2(4));--进位结果
				reg3(29 downto 4) <= reg2(30 downto 5);
			end if;
	end process bit2;
	
	bit3:process(clk,rst)
		begin
			if(rst = '1') then
				reg4 <= "00000000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg4(2 downto 0) <= reg3(2 downto 0);
				reg4(3) <= reg3(3) xor reg3(4) xor reg3(5);
				reg4(4) <= (reg3(3) and reg3(4)) or (reg3(4) and reg3(5)) or (reg3(3) and reg3(5));
				reg4(28 downto 5) <= reg3(29 downto 6);
			end if;
	end process bit3;
	
	bit4:process(clk,rst)
		begin
			if(rst = '1') then
				reg5 <= "0000000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg5(3 downto 0) <= reg4(3 downto 0);
				reg5(4) <= reg4(4) xor reg4(5) xor reg4(6);
				reg5(5) <= (reg4(4) and reg4(5)) or (reg4(4) and reg4(6)) or (reg4(6) and reg4(5));
				reg5(27 downto 6) <= reg4(28 downto 7);
			end if;
	end process bit4;
	
	

		bit5:process(clk,rst)
		begin
			if(rst = '1') then
				reg6 <= "000000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg6(4 downto 0) <= reg5(4 downto 0);
				reg6(5) <= reg5(5) xor reg5(6) xor reg5(7);
				reg6(6) <= (reg5(5) and reg5(6)) or (reg5(5) and reg5(7)) or (reg5(6) and reg5(7));
				reg6(26 downto 7) <= reg5(27 downto 8);
			end if;
	end process bit5;
	
		
		bit6:process(clk,rst)
		begin
			if(rst = '1') then
				reg7 <= "00000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg7(5 downto 0) <= reg6(5 downto 0);
				reg7(6) <= reg6(6) xor reg6(7) xor reg6(8);
				reg7(7) <= (reg6(6) and reg6(7)) or (reg6(8) and reg6(7)) or (reg6(6) and reg6(8));
				reg7(25 downto 8) <= reg6(26 downto 9);
			end if;
	end process bit6;
	
	bit7:process(clk,rst)
		begin
			if(rst = '1') then
				reg8 <= "0000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg8(6 downto 0) <= reg7(6 downto 0);
				reg8(7) <= reg7(7) xor reg7(9) xor reg7(8);
				reg8(8) <= (reg7(7) and reg7(8)) or (reg7(8) and reg7(9)) or (reg7(7) and reg7(9));
				reg8(24 downto 9) <= reg7(25 downto 10);
			end if;
	end process bit7;
	
	bit8:process(clk,rst)
		begin
			if(rst = '1') then
				reg9 <= "000000000000000000000000";
			elsif(rising_edge(clk)) then
				reg9(7 downto 0) <= reg8(7 downto 0);
				reg9(8) <= reg8(10) xor reg8(9) xor reg8(8);
				reg9(9) <= (reg8(10) and reg8(8)) or (reg8(8) and reg8(9)) or (reg8(10) and reg8(9));
				reg9(23 downto 10) <= reg8(24 downto 11);
			end if;
	end process bit8;
	
	
		bit9:process(clk,rst)
		begin
			if(rst = '1') then
				reg10 <= "00000000000000000000000";
			elsif(rising_edge(clk)) then
				reg10(8 downto 0) <= reg9(8 downto 0);
				reg10(9) <= reg9(10) xor reg9(9) xor reg9(11);
				reg10(10) <= (reg9(10) and reg9(9)) or (reg9(11) and reg9(9)) or (reg9(10) and reg9(11));
				reg10(22 downto 11) <= reg9(23 downto 12);
			end if;
	end process bit9;
	
	
	bit10:process(clk,rst)
		begin
			if(rst = '1') then
				reg11 <= "0000000000000000000000";
			elsif(rising_edge(clk)) then
				reg11(9 downto 0) <= reg10(9 downto 0);
				reg11(10) <= reg10(10) xor reg10(12) xor reg10(11);
				reg11(11) <= (reg10(10) and reg10(12)) or (reg10(11) and reg10(12)) or (reg10(10) and reg10(11));
				reg11(21 downto 12) <= reg10(22 downto 13);
			end if;
	end process bit10;
	
	bit11:process(clk,rst)
		begin
			if(rst = '1') then
				reg12 <= "000000000000000000000";
			elsif(rising_edge(clk)) then
				reg12(10 downto 0) <= reg11(10 downto 0);
				reg12(11) <= reg11(13) xor reg11(12) xor reg11(11);
				reg12(12) <= (reg11(13) and reg11(12)) or (reg11(11) and reg11(12)) or (reg11(13) and reg11(11));
				reg12(20 downto 13) <= reg11(21 downto 14);
			end if;
	end process bit11;
	
	
		bit12:process(clk,rst)
		begin
			if(rst = '1') then
				reg13 <= "00000000000000000000";
			elsif(rising_edge(clk)) then
				reg13(11 downto 0) <= reg12(11 downto 0);
				reg13(12) <= reg12(13) xor reg12(12) xor reg12(14);
				reg13(13) <= (reg12(13) and reg12(12)) or (reg12(14) and reg12(12)) or (reg12(13) and reg12(14));
				reg13(19 downto 14) <= reg12(20 downto 15);
			end if;
	end process bit12;
	
	
			bit13:process(clk,rst)
		begin
			if(rst = '1') then
				reg14 <= "0000000000000000000";
			elsif(rising_edge(clk)) then
				reg14(12 downto 0) <= reg13(12 downto 0);
				reg14(13) <= reg13(13) xor reg13(15) xor reg13(14);
				reg14(14) <= (reg13(13) and reg13(15)) or (reg13(14) and reg13(15)) or (reg13(13) and reg13(14));
				reg14(18 downto 15) <= reg13(19 downto 16);
			end if;
	end process bit13;
	
	
	bit14:process(clk,rst)
		begin
			if(rst = '1') then
				reg15 <= "000000000000000000";
			elsif(rising_edge(clk)) then
				reg15(13 downto 0) <= reg14(13 downto 0);
				reg15(14) <= reg14(16) xor reg14(15) xor reg14(14);
				reg15(15) <= (reg14(16) and reg14(15)) or (reg14(14) and reg14(15)) or (reg14(16) and reg14(14));
				reg15(17 downto 16) <= reg14(18 downto 17);
			end if;
	end process bit14;
	
-------------------------------------------------	
	sum_final:process(clk,rst)
		begin
			if(rst = '1') then
				sum <= "0000000000000000";
			elsif(rising_edge(clk)) then
				sum(14 downto 0) <= reg15(14 downto 0);
				sum(15) <= reg15(17) xor reg15(15) xor reg15(16);
				--sum(12) <= (reg11(11) and reg11(12)) or (reg11(11) and reg11(13)) or (reg11(12) and reg11(13));
			end if;
	end process sum_final;

end depict;