adder.sim.rpt

采用加法树流水线乘法构造八位乘法器

; |add|adder10:inst9|reg3[13]   ; |add|adder10:inst9|reg3[13]   ; out              ;
; |add|adder10:inst9|reg2[0]    ; |add|adder10:inst9|reg2[0]    ; out              ;
; |add|adder10:inst9|reg2[1]    ; |add|adder10:inst9|reg2[1]    ; out              ;
; |add|adder10:inst9|reg2[2]    ; |add|adder10:inst9|reg2[2]    ; out              ;
; |add|adder10:inst9|reg2[3]    ; |add|adder10:inst9|reg2[3]    ; out              ;
; |add|adder10:inst9|reg2[4]    ; |add|adder10:inst9|reg2[4]    ; out              ;
; |add|adder10:inst9|reg2[5]    ; |add|adder10:inst9|reg2[5]    ; out              ;
; |add|adder10:inst9|reg2[6]    ; |add|adder10:inst9|reg2[6]    ; out              ;
; |add|adder10:inst9|reg2[7]    ; |add|adder10:inst9|reg2[7]    ; out              ;
; |add|adder10:inst9|reg2[8]    ; |add|adder10:inst9|reg2[8]    ; out              ;
; |add|adder10:inst9|reg2[9]    ; |add|adder10:inst9|reg2[9]    ; out              ;
; |add|adder10:inst9|reg2[10]   ; |add|adder10:inst9|reg2[10]   ; out              ;
; |add|adder10:inst9|reg2[11]   ; |add|adder10:inst9|reg2[11]   ; out              ;
; |add|adder10:inst9|reg2[12]   ; |add|adder10:inst9|reg2[12]   ; out              ;
; |add|adder10:inst9|reg2[14]   ; |add|adder10:inst9|reg2[14]   ; out              ;
; |add|adder10:inst9|reg1[0]    ; |add|adder10:inst9|reg1[0]    ; out              ;
; |add|adder10:inst9|reg1[2]    ; |add|adder10:inst9|reg1[2]    ; out              ;
; |add|adder10:inst9|reg1[3]    ; |add|adder10:inst9|reg1[3]    ; out              ;
; |add|adder10:inst9|reg1[4]    ; |add|adder10:inst9|reg1[4]    ; out              ;
; |add|adder10:inst9|reg1[5]    ; |add|adder10:inst9|reg1[5]    ; out              ;
; |add|adder10:inst9|reg1[6]    ; |add|adder10:inst9|reg1[6]    ; out              ;
; |add|adder10:inst9|reg1[7]    ; |add|adder10:inst9|reg1[7]    ; out              ;
; |add|adder10:inst9|reg1[8]    ; |add|adder10:inst9|reg1[8]    ; out              ;
; |add|adder10:inst9|reg1[9]    ; |add|adder10:inst9|reg1[9]    ; out              ;
; |add|adder10:inst9|reg1[10]   ; |add|adder10:inst9|reg1[10]   ; out              ;
; |add|adder10:inst9|reg1[11]   ; |add|adder10:inst9|reg1[11]   ; out              ;
; |add|adder10:inst9|reg1[12]   ; |add|adder10:inst9|reg1[12]   ; out              ;
; |add|adder10:inst9|reg1[13]   ; |add|adder10:inst9|reg1[13]   ; out              ;
; |add|adder10:inst9|reg1[15]   ; |add|adder10:inst9|reg1[15]   ; out              ;
; |add|tran10to12:inst11|b[2]   ; |add|tran10to12:inst11|b[2]   ; out              ;
; |add|tran10to12:inst11|b[3]   ; |add|tran10to12:inst11|b[3]   ; out              ;
; |add|tran10to12:inst11|b[4]   ; |add|tran10to12:inst11|b[4]   ; out              ;
; |add|tran10to12:inst11|b[5]   ; |add|tran10to12:inst11|b[5]   ; out              ;
; |add|tran10to12:inst11|a[0]   ; |add|tran10to12:inst11|a[0]   ; out              ;
; |add|tran10to12:inst11|a[1]   ; |add|tran10to12:inst11|a[1]   ; out              ;
; |add|tran10to12:inst11|a[2]   ; |add|tran10to12:inst11|a[2]   ; out              ;
; |add|tran10to12:inst11|a[3]   ; |add|tran10to12:inst11|a[3]   ; out              ;
; |add|tran10to12:inst11|a[4]   ; |add|tran10to12:inst11|a[4]   ; out              ;
; |add|tran10to12:inst11|a[5]   ; |add|tran10to12:inst11|a[5]   ; out              ;
; |add|tran10to12:inst11|a[6]   ; |add|tran10to12:inst11|a[6]   ; out              ;
; |add|tran10to12:inst11|a[7]   ; |add|tran10to12:inst11|a[7]   ; out              ;
; |add|tran10to12:inst11|a[8]   ; |add|tran10to12:inst11|a[8]   ; out              ;
; |add|adder13:inst12|reg3~1    ; |add|adder13:inst12|reg3~1    ; out0             ;
; |add|adder13:inst12|reg3~5    ; |add|adder13:inst12|reg3~5    ; out0             ;
; |add|adder13:inst12|reg4~0    ; |add|adder13:inst12|reg4~0    ; out0             ;
; |add|adder13:inst12|reg4~1    ; |add|adder13:inst12|reg4~1    ; out0             ;
; |add|adder13:inst12|reg4~5    ; |add|adder13:inst12|reg4~5    ; out0             ;
; |add|adder13:inst12|reg4~6    ; |add|adder13:inst12|reg4~6    ; out0             ;
; |add|adder13:inst12|reg5~0    ; |add|adder13:inst12|reg5~0    ; out0             ;
; |add|adder13:inst12|reg5~1    ; |add|adder13:inst12|reg5~1    ; out0             ;
; |add|adder13:inst12|reg5~2    ; |add|adder13:inst12|reg5~2    ; out0             ;
; |add|adder13:inst12|reg5~3    ; |add|adder13:inst12|reg5~3    ; out0             ;
; |add|adder13:inst12|reg5~4    ; |add|adder13:inst12|reg5~4    ; out0             ;
; |add|adder13:inst12|reg5~5    ; |add|adder13:inst12|reg5~5    ; out0             ;
; |add|adder13:inst12|reg5~6    ; |add|adder13:inst12|reg5~6    ; out0             ;
; |add|adder13:inst12|reg6~0    ; |add|adder13:inst12|reg6~0    ; out0             ;
; |add|adder13:inst12|reg6~1    ; |add|adder13:inst12|reg6~1    ; out0             ;
; |add|adder13:inst12|reg7~0    ; |add|adder13:inst12|reg7~0    ; out0             ;
; |add|adder13:inst12|reg7~1    ; |add|adder13:inst12|reg7~1    ; out0             ;
; |add|adder13:inst12|reg8~1    ; |add|adder13:inst12|reg8~1    ; out0             ;
; |add|adder13:inst12|sum[0]    ; |add|adder13:inst12|sum[0]    ; out              ;
; |add|adder13:inst12|sum[1]    ; |add|adder13:inst12|sum[1]    ; out              ;
; |add|adder13:inst12|sum[2]    ; |add|adder13:inst12|sum[2]    ; out              ;
; |add|adder13:inst12|sum[3]    ; |add|adder13:inst12|sum[3]    ; out              ;
; |add|adder13:inst12|sum[4]    ; |add|adder13:inst12|sum[4]    ; out              ;
; |add|adder13:inst12|sum[5]    ; |add|adder13:inst12|sum[5]    ; out              ;
; |add|adder13:inst12|sum[6]    ; |add|adder13:inst12|sum[6]    ; out              ;
; |add|adder13:inst12|sum[7]    ; |add|adder13:inst12|sum[7]    ; out              ;
; |add|adder13:inst12|reg11[0]  ; |add|adder13:inst12|reg11[0]  ; out              ;
; |add|adder13:inst12|reg11[1]  ; |add|adder13:inst12|reg11[1]  ; out              ;
; |add|adder13:inst12|reg11[2]  ; |add|adder13:inst12|reg11[2]  ; out              ;
; |add|adder13:inst12|reg11[3]  ; |add|adder13:inst12|reg11[3]  ; out              ;
; |add|adder13:inst12|reg11[4]  ; |add|adder13:inst12|reg11[4]  ; out              ;
; |add|adder13:inst12|reg11[5]  ; |add|adder13:inst12|reg11[5]  ; out              ;
; |add|adder13:inst12|reg11[6]  ; |add|adder13:inst12|reg11[6]  ; out              ;
; |add|adder13:inst12|reg11[7]  ; |add|adder13:inst12|reg11[7]  ; out              ;
; |add|adder13:inst12|reg10[0]  ; |add|adder13:inst12|reg10[0]  ; out              ;
; |add|adder13:inst12|reg10[1]  ; |add|adder13:inst12|reg10[1]  ; out              ;
; |add|adder13:inst12|reg10[2]  ; |add|adder13:inst12|reg10[2]  ; out              ;
; |add|adder13:inst12|reg10[3]  ; |add|adder13:inst12|reg10[3]  ; out              ;
; |add|adder13:inst12|reg10[4]  ; |add|adder13:inst12|reg10[4]  ; out              ;
; |add|adder13:inst12|reg10[5]  ; |add|adder13:inst12|reg10[5]  ; out              ;
; |add|adder13:inst12|reg10[6]  ; |add|adder13:inst12|reg10[6]  ; out              ;
; |add|adder13:inst12|reg10[7]  ; |add|adder13:inst12|reg10[7]  ; out              ;
; |add|adder13:inst12|reg9[0]   ; |add|adder13:inst12|reg9[0]   ; out              ;
; |add|adder13:inst12|reg9[1]   ; |add|adder13:inst12|reg9[1]   ; out              ;
; |add|adder13:inst12|reg9[2]   ; |add|adder13:inst12|reg9[2]   ; out              ;
; |add|adder13:inst12|reg9[3]   ; |add|adder13:inst12|reg9[3]   ; out              ;
; |add|adder13:inst12|reg9[4]   ; |add|adder13:inst12|reg9[4]   ; out              ;
; |add|adder13:inst12|reg9[5]   ; |add|adder13:inst12|reg9[5]   ; out              ;
; |add|adder13:inst12|reg9[6]   ; |add|adder13:inst12|reg9[6]   ; out              ;
; |add|adder13:inst12|reg9[7]   ; |add|adder13:inst12|reg9[7]   ; out              ;
; |add|adder13:inst12|reg8[0]   ; |add|adder13:inst12|reg8[0]   ; out              ;
; |add|adder13:inst12|reg8[1]   ; |add|adder13:inst12|reg8[1]   ; out              ;
; |add|adder13:inst12|reg8[2]   ; |add|adder13:inst12|reg8[2]   ; out              ;
; |add|adder13:inst12|reg8[3]   ; |add|adder13:inst12|reg8[3]   ; out              ;
; |add|adder13:inst12|reg8[4]   ; |add|adder13:inst12|reg8[4]   ; out              ;
; |add|adder13:inst12|reg8[5]   ; |add|adder13:inst12|reg8[5]   ; out              ;
; |add|adder13:inst12|reg8[6]   ; |add|adder13:inst12|reg8[6]   ; out              ;
; |add|adder13:inst12|reg8[7]   ; |add|adder13:inst12|reg8[7]   ; out              ;
; |add|adder13:inst12|reg8[9]   ; |add|adder13:inst12|reg8[9]   ; out              ;
; |add|adder13:inst12|reg7[0]   ; |add|adder13:inst12|reg7[0]   ; out              ;
; |add|adder13:inst12|reg7[1]   ; |add|adder13:inst12|reg7[1]   ; out              ;
; |add|adder13:inst12|reg7[2]   ; |add|adder13:inst12|reg7[2]   ; out              ;
; |add|adder13:inst12|reg7[3]   ; |add|adder13:inst12|reg7[3]   ; out              ;
; |add|adder13:inst12|reg7[4]   ; |add|adder13:inst12|reg7[4]   ; out              ;
; |add|adder13:inst12|reg7[5]   ; |add|adder13:inst12|reg7[5]   ; out              ;
; |add|adder13:inst12|reg7[6]   ; |add|adder13:inst12|reg7[6]   ; out              ;
; |add|adder13:inst12|reg7[8]   ; |add|adder13:inst12|reg7[8]   ; out              ;
; |add|adder13:inst12|reg7[10]  ; |add|adder13:inst12|reg7[10]  ; out              ;
; |add|adder13:inst12|reg6[0]   ; |add|adder13:inst12|reg6[0]   ; out              ;
; |add|adder13:inst12|reg6[1]   ; |add|adder13:inst12|reg6[1]   ; out              ;
; |add|adder13:inst12|reg6[2]   ; |add|adder13:inst12|reg6[2]   ; out              ;
; |add|adder13:inst12|reg6[3]   ; |add|adder13:inst12|reg6[3]   ; out              ;
; |add|adder13:inst12|reg6[4]   ; |add|adder13:inst12|reg6[4]   ; out              ;
; |add|adder13:inst12|reg6[5]   ; |add|adder13:inst12|reg6[5]   ; out              ;
; |add|adder13:inst12|reg6[7]   ; |add|adder13:inst12|reg6[7]   ; out              ;
; |add|adder13:inst12|reg6[9]   ; |add|adder13:inst12|reg6[9]   ; out              ;
; |add|adder13:inst12|reg6[11]  ; |add|adder13:inst12|reg6[11]  ; out              ;
; |add|adder13:inst12|reg5[0]   ; |add|adder13:inst12|reg5[0]   ; out              ;
; |add|adder13:inst12|reg5[1]   ; |add|adder13:inst12|reg5[1]   ; out              ;
; |add|adder13:inst12|reg5[2]   ; |add|adder13:inst12|reg5[2]   ; out              ;
; |add|adder13:inst12|reg5[3]   ; |add|adder13:inst12|reg5[3]   ; out              ;
; |add|adder13:inst12|reg5[4]   ; |add|adder13:inst12|reg5[4]   ; out              ;
; |add|adder13:inst12|reg5[5]   ; |add|adder13:inst12|reg5[5]   ; out              ;
; |add|adder13:inst12|reg5[6]   ; |add|adder13:inst12|reg5[6]   ; out              ;
; |add|adder13:inst12|reg5[7]   ; |add|adder13:inst12|reg5[7]   ; out              ;
; |add|adder13:inst12|reg5[8]   ; |add|adder13:inst12|reg5[8]   ; out              ;
; |add|adder13:inst12|reg5[10]  ; |add|adder13:inst12|reg5[10]  ; out              ;
; |add|adder13:inst12|reg5[12]  ; |add|adder13:inst12|reg5[12]  ; out              ;
; |add|adder13:inst12|reg4[0]   ; |add|adder13:inst12|reg4[0]   ; out              ;
; |add|adder13:inst12|reg4[1]   ; |add|adder13:inst12|reg4[1]   ; out              ;
; |add|adder13:inst12|reg4[2]   ; |add|adder13:inst12|reg4[2]   ; out              ;
; |add|adder13:inst12|reg4[3]   ; |add|adder13:inst12|reg4[3]   ; out              ;
; |add|adder13:inst12|reg4[4]   ; |add|adder13:inst12|reg4[4]   ; out              ;
; |add|adder13:inst12|reg4[5]   ; |add|adder13:inst12|reg4[5]   ; out              ;
; |add|adder13:inst12|reg4[6]   ; |add|adder13:inst12|reg4[6]   ; out              ;
; |add|adder13:inst12|reg4[7]   ; |add|adder13:inst12|reg4[7]   ; out              ;
; |add|adder13:inst12|reg4[8]   ; |add|adder13:inst12|reg4[8]   ; out              ;
; |add|adder13:inst12|reg4[9]   ; |add|adder13:inst12|reg4[9]   ; out              ;
; |add|adder13:inst12|reg4[11]  ; |add|adder13:inst12|reg4[11]  ; out              ;
; |add|adder13:inst12|reg4[13]  ; |add|adder13:inst12|reg4[13]  ; out              ;
; |add|adder13:inst12|reg3[0]   ; |add|adder13:inst12|reg3[0]   ; out              ;
; |add|adder13:inst12|reg3[1]   ; |add|adder13:inst12|reg3[1]   ; out              ;
; |add|adder13:inst12|reg3[2]   ; |add|adder13:inst12|reg3[2]   ; out              ;
; |add|adder13:inst12|reg3[3]   ; |add|adder13:inst12|reg3[3]   ; out              ;
; |add|adder13:inst12|reg3[4]   ; |add|adder13:inst12|reg3[4]   ; out              ;
; |add|adder13:inst12|reg3[5]   ; |add|adder13:inst12|reg3[5]   ; out              ;
; |add|adder13:inst12|reg3[6]   ; |add|adder13:inst12|reg3[6]   ; out              ;
; |add|adder13:inst12|reg3[7]   ; |add|adder13:inst12|reg3[7]   ; out              ;
; |add|adder13:inst12|reg3[8]   ; |add|adder13:inst12|reg3[8]   ; out              ;
; |add|adder13:inst12|reg3[9]   ; |add|adder13:inst12|reg3[9]   ; out              ;
; |add|adder13:inst12|reg3[10]  ; |add|adder13:inst12|reg3[10]  ; out              ;
; |add|adder13:inst12|reg3[12]  ; |add|adder13:inst12|reg3[12]  ; out              ;