adder.map.rpt

采用加法树流水线乘法构造八位乘法器

Analysis & Synthesis report for adder
Thu Apr 02 14:08:48 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Source assignments for adder16:inst13|altshift_taps:reg13_rtl_0|shift_taps_d0m:auto_generated|altsyncram_g681:altsyncram2
 10. Source assignments for adder16:inst13|altshift_taps:reg12_rtl_1|shift_taps_e0m:auto_generated|altsyncram_k681:altsyncram2
 11. Source assignments for adder16:inst13|altshift_taps:reg11_rtl_2|shift_taps_q1m:auto_generated|altsyncram_c981:altsyncram2
 12. Source assignments for adder16:inst13|altshift_taps:reg10_rtl_3|shift_taps_g0m:auto_generated|altsyncram_q681:altsyncram2
 13. Source assignments for adder16:inst13|altshift_taps:reg9_rtl_4|shift_taps_f0m:auto_generated|altsyncram_l681:altsyncram2
 14. Source assignments for adder16:inst13|altshift_taps:reg7_rtl_5|shift_taps_73m:auto_generated|altsyncram_q981:altsyncram2
 15. Source assignments for adder16:inst13|altshift_taps:reg6_rtl_6|shift_taps_l1m:auto_generated|altsyncram_o681:altsyncram2
 16. Source assignments for adder16:inst13|altshift_taps:reg5_rtl_7|shift_taps_b3m:auto_generated|altsyncram_ic81:altsyncram2
 17. Source assignments for adder13:inst1|altshift_taps:sum_rtl_8|shift_taps_83m:auto_generated|altsyncram_ac81:altsyncram2
 18. Source assignments for adder13:inst12|altshift_taps:sum_rtl_9|shift_taps_93m:auto_generated|altsyncram_ec81:altsyncram2
 19. Source assignments for adder13:inst1|altshift_taps:reg3_rtl_10|shift_taps_r1m:auto_generated|altsyncram_k981:altsyncram2
 20. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg13_rtl_0
 21. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg12_rtl_1
 22. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg11_rtl_2
 23. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg10_rtl_3
 24. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg9_rtl_4
 25. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg7_rtl_5
 26. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg6_rtl_6
 27. Parameter Settings for Inferred Entity Instance: adder16:inst13|altshift_taps:reg5_rtl_7
 28. Parameter Settings for Inferred Entity Instance: adder13:inst1|altshift_taps:sum_rtl_8
 29. Parameter Settings for Inferred Entity Instance: adder13:inst12|altshift_taps:sum_rtl_9
 30. Parameter Settings for Inferred Entity Instance: adder13:inst1|altshift_taps:reg3_rtl_10
 31. altshift_taps Parameter Settings by Entity Instance
 32. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Apr 02 14:08:48 2009    ;
; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name                      ; adder                                    ;
; Top-level Entity Name              ; add                                      ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 289                                      ;
; Total registers                    ; 289                                      ;
; Total pins                         ; 34                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 821                                      ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C70F896C6       ;                    ;
; Top-level entity name                                              ; add                ; adder              ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;