tran8to9.vhd

来自「采用加法树流水线乘法构造八位乘法器」· VHDL 代码 · 共 26 行

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity tran8to9 is 
	port(
		a8,b8:		in std_logic_vector(7 downto 0);
		clk:        in std_logic;
		a9,b9:		out std_logic_vector(8 downto 0));
end entity tran8to9;

architecture beha of tran8to9 is
signal  a,b:std_logic_vector(8 downto 0);
begin
a9<=a;
b9<=b;
process(clk)
		begin	
		if(rising_edge(clk)) then
	           a<='0'&a8;
	           b<=b8&'0';
	end if;
end process;
end beha;